Results 61 to 70 of about 138 (136)
AN EXHAUSTIVE ANALYSIS OF SEU EFFECTS IN THE SRAM MEMORY OF SOFT PROCESSOR [PDF]
The Embedded system design is characterized by its daily complexity. It integrates a hardware and software parts together on a common platform. These parts may be defective by a spurious signal, subsequently found to be two types of errors.
AFEF KCHAOU +3 more
doaj
Impact of Fabrication Defects on FPGA Logic Using Memristor-Based Memory Cells
Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory.
Jonas Schoenen +10 more
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In this paper, we propose Automatic Configuration Memory Fault Injection (ACMFI), a tool that calculates the architectural vulnerability factor (AVF) and soft error rate (SER) using the emulation fault injection technique. SER, which is essential for the
Dongmin Lee +4 more
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With the shrinking feature sizes of static random access memory-based field programmable gate arrays (FPGAs), the occurrence probability of multiple-cell upsets (MCUs) in FPGAs continues to increase. This reduces the reliability of FPGAs.
Yue Li +3 more
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FPGA-based fault injection design for 16K-point FFT processor
There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
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We are pleased to present this new issue of the journal featuring four compelling papers that highlight significant advancements across integrated circuit simulation, high-efficiency digital signal processing architectures, reliable memory design ...
Mladen Knezic
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Energy-efficient scalable memory LSTM cell with approximate feature processing units
Classification of time series-based features, such as speech and face recognition, effectively uses long and short-term dependencies through four unique gates. Thus, four matrix-vector multiplication (MVM) operations are necessary.
R Sindhu, Arunachalam V
doaj +1 more source
HyST-DNA: Hybrid SRAM-TCAM DNN accelerator with genetic optimization on FPGA
Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments.
Vandana Thakur +2 more
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An Area-Time Efficient Hardware Architecture for ML-KEM Post-Quantum Cryptography Standard
To facilitate the integration of the NIST-standardized post-quantum cryptographic (PQC) algorithm, Module Lattice-based Key Encapsulation Mechanism (ML-KEM), into quantum-resistant devices and cryptosystems, this study introduces an area-time efficient ...
Trong-Hung Nguyen +6 more
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The emergence of large-scale quantum computers threatens the long-term security of classical public-key cryptosystems, making the integration of post-quantum cryptography (PQC) essential for resource-constrained embedded and IoT platforms.
Tri-Duc Ta +3 more
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