Results 81 to 90 of about 37,708 (227)
, 2013 本实用新型属于电学领域，涉及了一种基于SRAM（静态存储器）架构FPGA复位电路。该复位电路包括FPGA以及复位芯片，其中，FPGA的配置成功标志信号管脚接口与复位芯片的复位输入端管脚连接；复位芯片的复位输出管脚与FPGA的一个全局时钟输入管脚连接 ...
王华伟 +4 more
core
Sketch-based data plane hardware model for software-defined measurement
Tongxin xuebao, 2017 A sketch-based data plane hardware model for software-defined measurement was introduced,and it was implemented in the programmable network device NetMagic.A generic sketch model for collecting flow-level data using high-speed memories on the FPGA was ...
Mian DAI, Guang CHENG
doaj +2 more sources
Yuanzineng kexue jishuTo investigate the effects of atmospheric neutron radiation effects on a system-in-package (SiP) device, single event upset (SEU) and single event functional interruption (SEFI) were focused on in the experiment.
YE Jiefeng1, 2, LIANG Chaohui2, ZHANG Zhangang2, ZHENG Shunshun1, 2, LEI Zhifeng2, LIU Zhili3, GENG Gaoying3, HAN Hui1
doaj +1 more source
Innovative Hardware Accelerator Architecture for FPGA‐Based General‐Purpose RISC Microprocessors
Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.Reconfigurable computing (RC) theory aims to take advantage of the flexibility of general‐purpose processors (GPPs) alongside the performance of application specific integrated circuits (ASICs). Numerous RC architectures have been proposed since the 1960s, but all are struggling to become mainstream.
Ehsan Ali, Iouliia Skliarova
wiley +1 more source
Comparative Analysis of On-Chip FPGA Memory Architectures for Viterbi Decoder Implementation in DVB Systems [PDF]
JES: Journal of Engineering SciencesHigh-definition Digital Video Broadcasting (DVB) systems demand high data rates, resulting in increased hardware complexity and power consumption, with the Viterbi decoder (VD) being a key contributor.
Asmaa Mosbeh +3 more
doaj +1 more source
A prototype parallel multi-FPGA accelerator for SPICE CMOS model evaluation
, 2011 Due to ever increasing complexity of circuits, EDA tools and algorithms are demanding more computational power. This made transistor-level simulation a growing bottleneck in the circuit development process.
Maache, Ahmed
core
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs
, 2012 We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic ...
Ting-Jung Lin +7 more
core +1 more source
AN EXHAUSTIVE ANALYSIS OF SEU EFFECTS IN THE SRAM MEMORY OF SOFT PROCESSOR [PDF]
Journal of Engineering Science and Technology, 2018 The Embedded system design is characterized by its daily complexity. It integrates a hardware and software parts together on a common platform. These parts may be defective by a spurious signal, subsequently found to be two types of errors.
AFEF KCHAOU +3 more
doaj
Dynamically reconfigurable hardware for embedded control systems
, 2012 Paiz Gatica CV. Dynamically reconfigurable hardware for embedded control systems. Bielefeld: Universität; 2012.This thesis explores the use of dynamically reconfigurable hardware for the realisation of embedded control systems, using the most well-known ...
Paiz Gatica, Carlos Vladimir
core
An FPGA Based Adaptive Weightless Neural Network Hardware [PDF]
, 2008 This paper explores the significant practical difficulties inherent in mapping large artificial neural structures onto digital hardware. Specifically, a class of weightless neural architecture called the Enhanced Probabilistic Convergent Network is ...
Howells, Gareth +6 more
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