Results 81 to 90 of about 138 (136)

Power estimation approach for SRAM-based FPGAs

Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family.
Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel   +4 more
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On the Static Cross Section of SRAM-Based FPGAs

2008 IEEE Radiation Effects Data Workshop, 2008
We present new experimental results about the sensitivity of SRAM-based FPGAs to heavy ions. We analyze the static cross section as a function of the FPGA resource type. We also study the soft error rate as function of the accumulated total dose, and investigate the occurrence of multiple bit upsets in the configuration memory.
MANUZZATO, ANDREA, GERARDIN, SIMONE, PACCAGNELLA, ALESSANDRO, Sterpone, L., Violante, M.   +4 more
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A diagnosis method for interconnects in SRAM based FPGAs

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), 2002
This paper presents a five-step programming method to diagnose faults in FPGA interconnection resources. A single and a multiple fault model are given. The accuracy of fault location is a single segment for a segment stuck-at fault or a segment open fault, a segment pair or terminal pair for bridge fault or switch stuck-off fault under the single fault
Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi   +3 more
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An XDL Analysis Method for SRAM-Based FPGA

2016
Soft errors due to single event upsets (SEUs) are the main challenge to the reliability of SRAM-based FPGA designs. To calculate the soft error rate, the XDL information, such as the sensitive configuration bits, signal propagation, is needed to be acquired. In this paper, an XDL analysis method for SRAM-based FPGA is presented.
Junfeng Liu, Yunyi Yan, Jinfu Wu
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Power Optimization Techniques for SRAM-Based FPGAs

2006 International Conference on Field Programmable Logic and Applications, 2006
In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-Vdd ...
Somsubhra Mondal, Seda Ogrenci Memik
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Reconfigurable Fault Tolerant Processor on a SRAM based FPGA

2020 IEEE International Conference on Electro Information Technology (EIT), 2020
The hardware of the satellite system is mission-critical of the whole system. The commercial off-the-shelf (COTS) components are commonly used in satellite systems due to their low cost. They are not hardened to withstand the space-born radiation, and thus, may fail, jeopardizing the entire mission.
Bhargav Shashidhara, Shrikant Jadhav, Youngsoo Kim 0001   +2 more
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Analyzing SEU effects is SRAM-based FPGAsb

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2003
Commercial-off-the-shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory.
VIOLANTE, MASSIMO, CESCHIA, M., SONZA REORDA, Matteo, PACCAGNELLA, A., BERNARDI, PAOLO, REBAUDENGO, Maurizio, BORTOLATO, D., BELLATO, M., ZAMBOLIN, P., CANDELORI, A.   +9 more
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Testing embedded RAM modules in SRAM-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, 2006
This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration.
Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali   +2 more
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Efficient estimation of SEU effects in SRAM-based FPGAs

11th IEEE International On-Line Testing Symposium, 2005
SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to single event upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs' configuration memory.
SONZA REORDA, Matteo, STERPONE, Luca, VIOLANTE, MASSIMO   +2 more
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Dependability issues in SRAM-based FPGA design

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
- tutorial a la conference qui a eu lieu en Decembre 2007 a Marrakech, Maroc, sur le theme "".
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