Results 161 to 170 of about 10,751 (237)

A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM. [PDF]

Micromachines (Basel)
Jiang X, Jia X, Wang S, Guo Y, Guo F, Long X, Geng L, Yang J, Liu M.   +8 more
europepmc   +1 more source

Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection. [PDF]

Micromachines (Basel)
Xu J, Pu H, Wang D.
europepmc   +1 more source

Monolithic 3D Oscillatory Ising Machine Using Reconfigurable FeFET Routing for Large-Scalability and Low-Power Consumption. [PDF]

Adv Sci (Weinh)
Kim JP, Kuk SH, Kim HW, Jeong J, Park J, Kim BH, Kim J, Todri-Sanial A, Kim S.   +8 more
europepmc   +1 more source

From Printed Devices to Vertically Stacked, 3D Flexible Hybrid Systems. [PDF]

Adv Mater
Liu F, Christou A, Dahiya AS, Dahiya R.
europepmc   +1 more source

Physical unclonable in-memory computing for simultaneous protecting private data and deep learning models. [PDF]

Nat Commun
Yue W, Wu K, Li Z, Zhou J, Wang Z, Zhang T, Yang Y, Ye L, Wu Y, Bu W, Wang S, He X, Yan X, Tao Y, Yan B, Huang R, Yang Y.   +16 more
europepmc   +1 more source

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines. [PDF]

Sci Adv
Xu Y, Zhao Z, Xiao Y, Yu T, Mulaosmanovic H, Kleimaier D, Duenkel S, Beyer S, Gong X, Joshi R, Hu X, Wen S, Rios AS, Lekkala K, Itti L, Homan E, George S, Narayanan V, Ni K.   +18 more
europepmc   +1 more source

Yield-Aware Leakage Power Reduction of On-Chip SRAMs

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An SRAM Test Quality Improvement Method For Automotive chips

2021 IEEE International Test Conference in Asia (ITC-Asia), 2021
Junlin Huang
exaly   +2 more sources

Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry

26th IEEE VLSI Test Symposium (vts 2008), 2008
In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures.
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae‐Joon Kim, Ching-Te Chuang, Kaushik Roy   +4 more
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A chip-stacked memory for on-chip SRAM-rich SoCs and processors

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009
Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a
Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno   +8 more
openaire   +1 more source