Results 171 to 180 of about 10,751 (237)

An on-chip test scheme for SRAMs

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test, 2002
Semiconductor technology continues to progress dramatically. With the increasing density, the testing of RAM chips has become progressively more difficult. In this paper, a new approach to simplify the testing of large SRAMs (static RAMs), embedded in VLSI chips or as stand-alone chips, by incorporating additional circuitry is proposed. >
P.K. Lala, A. Walker
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SRAM-Based Unique Chip Identifier Techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells.
Srivatsan Chellappa, Lawrence T. Clark
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An on-chip circuit for timing measurement of SRAM IP

2017 IEEE 12th International Conference on ASIC (ASICON), 2017
The timing of silicon IPs should be measured before they are integrated into chips. Embedded solutions are needed for timing measurement of silicon IPs. This paper introduces a circuit design for timing measurement of SRAM IP. A new circuit is designed for the measurement of setup time, hold time and access time.
Xianjie Long, Qin Wang 0009, Jianfei Jiang 0001, Nin Guan   +3 more
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Design and test of an SRAM chip

2013 IEEE 10th International Conference on ASIC, 2013
A fully customized 8×8 bits SRAM chip, based on Chartered 0.35 um EEPROM CMOS technology, is designed and taped-out for low-power and low-cost electronic equipment. According to test results, when the supply voltage is 3.3 V and clock frequency is 20 MHz, the chip can work correctly, and the performance reaches the design specifications, the access ...
Wenbin Liu, Jinhui Wang, Ligang Hou, Hongyan Yang, Jianbo Kang   +4 more
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An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Journal of Electronic Testing, 2014
The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime.
Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes   +4 more
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A scheme for multiple on-chip signature checking for embedded SRAMs

Proceedings European Design and Test Conference. ED & TC 97, 2000
Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a challenge to a system test engineer, due to its limited controllability and observability.
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar   +2 more
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BIST method of SRAM for network-on-chip

2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI), 2015
Network-on-chip (NoC) is becoming promising communication architecture for the next-generation system on chips. Intellectual property (IP) core is an important part of NoC system, this paper puts SRAM as an IP core to complete the test study of SRAM. We present a Built-in self-test (BIST) method for SRAM of network-on-chip based on reusing network-on ...
null Xu Chuanpei, null Tao Yi, null Wan Chunting   +2 more
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On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available.
Pankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini   +3 more
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Challenging on-chip SRAM security with boot-state statistics

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2017
On-chip memory is regarded by most secure system designers as a safe memory space, beyond the eyes of all but the most sophisticated attackers. Once a value is overwritten or the power has been removed, it is assumed that the data stored inside fully ceases to persist.
Joseph McMahan, Weilong Cui, Liang Xia, Jeff Heckey, Frederic T. Chong, Timothy Sherwood   +5 more
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Experimental fault analysis of 1 Mb SRAM chips

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 2002
Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that I/sub dd/=4.5 I; temperature=70/spl deg/C, and load capacity C/sub L/=30 pF,
Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki   +2 more
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