Results 191 to 200 of about 855 (207)

A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips

IEEE Transactions on Circuits and Systems II: Express Briefs, 2010
Meng-Fan Chang, Chien-Fu Chen
exaly  

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

2021
Ta-Wei Liu, Ping-Chun Wu, Shyh-Shyuan Sheu   +2 more
exaly  

Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

Journal of Applied Physics, 2012
Shinobu Fujita
exaly  

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

IEEE Journal of Solid-State Circuits, 2017
Taejoong Song, Woojin Rim, Yongho Kim
exaly  

Design of SRAM Based Interface Module with DMA in Inductive-Coupling 3D Stacked IoT Chips

2022
exaly  

A 15Kb 1.5 ns Access On-chip Tag SRAM

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications, 2005
P.F. Lu, S.P. Kowalcyzk, A.P. Pelella, W.V. Huott, U. Bakhru, J. Rawlins, P. Patel, Y.H. Chan, K.A. Jenkins   +8 more
openaire   +1 more source

Towards SRAM leakage power minimization by aggressive standby voltage scaling — Experiments on 40nm test chips

2017
Xin Fan, Tobias Gemmeke
exaly  

Junctionless 6T SRAM cell

Electronics Letters, 2010
A Kranti, I Ferain, Nima Dehdashti Akhavan   +2 more
exaly  

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

IEEE Transactions on Computers, 2009
Daniel Holcomb, Kevin Fu, Wayne P Burleson   +2 more
exaly  

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

2020
Yung-Ning Tu, Jing-Hong Wang, Ta-Wei Liu   +2 more
exaly