Results 221 to 230 of about 6,766 (248)

Stack and Queue Layouts for Toruses and Extended Hypercubes

2010 43rd Hawaii International Conference on System Sciences, 2010
Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses.
Saïd Bettayeb, Mohammad Hossain Heydari, Linda Morales, Ivan Hal Sudborough   +3 more
openaire   +1 more source

Space-efficient layouts for block stacking warehouses

IISE Transactions, 2019
In block stacking warehouses, pallets of Stock Keeping Units (SKUs) are stacked on top of one another in lanes on the warehouse floor.
Shahab Derhami, Jeffrey S. Smith, Kevin R. Gue   +2 more
openaire   +1 more source

Automatic generation of transistor stacks for cmos analog layout

1993 IEEE International Symposium on Circuits and Systems, 2002
A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function ...
Valentino Liberali, Enrico Malavasi, Davide Pandini   +2 more
openaire   +1 more source

Full stacked layout of analogue cells

IEEE International Symposium on Circuits and Systems, 2003
A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors.
U. Gatti, F. Maloberti, V. Liberali
openaire   +1 more source

Optimum stacked layout for analog CMOS ICs

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002
A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms.
E. Malavasi, D. Pandini, V. Liberali
openaire   +1 more source

An Analytical GPU-Enabled Framework for the Stacked 3D IC Layouts

Journal of Circuits, Systems and Computers
Three-dimensional integrated circuits (3D ICs) have recently garnered significant attention as a potential solution to the challenges posed by interconnect scaling in 2D ICs. However, the inclusion of an extra dimension and the introduction of through-silicon vias (TSVs) for interlayer connections have resulted in a significantly more complex compared
Xin Cheng 0004, Jinjia Zhou, Zhiqiang Zhang, Wenxin Yu 0001   +3 more
openaire   +1 more source

Analysis and modeling of layout scaling in silicon integrated stacked transformers

IEEE Transactions on Microwave Theory and Techniques, 2006
The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss).
T. BIONDI, SCUDERI, ANGELO, RAGONESE, EGIDIO, PALMISANO, Giuseppe   +3 more
openaire   +2 more sources

A support-design tool for block-stacking storage system layout

2017
In warehousing system, block stacking is one of the most common storage mode to guarantee high storage density in case of large quantities and limited product variety. Most common applications for block stacking storage are end-of-line warehouses at manufacturing facilities in processing industry (e.g., beverage, bakery, tissue industries).
Accorsi, R., Baruffaldi, G., Galizia, F. G., Manzini, R., Maranesi, F.   +4 more
openaire   +3 more sources

Thermal layout optimization for 3D stacked multichip modules

Microelectronics Journal, 2023
Yanning Chen, Dongyan Zhao 0002, Fang Liu, Jie Gao, Hui Zhu   +4 more
openaire   +1 more source

3D Perception Framework for Stacked Container Layout in the Physical Internet

2018
The Physical Internet concept was developed to address the current unsustainability problem of logistic systems. The key elements are the encapsulation and the handling of world-standard smart green modular containers (π-containers) throughout an open global logistic infrastructure.
Dong-Seong Kim, Hoa Tran-Dang
openaire   +1 more source