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Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization
2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2019 Memory corruption vulnerabilities in type-unsafe languages are often exploited to perform a control-flow hijacking attack, in which an attacker uses vulnerabilities to corrupt control data in the program to eventually gain control over the execution of ...
Misiker Tadesse Aga, T. Austin
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Detecting Stack Layout Corruptions with Robust Stack Unwinding
International Symposium on Recent Advances in Intrusion Detection, 2016The stack is a critical memory structure to ensure the correct execution of programs because control flow changes through the data stored in it, such as return addresses and function pointers. Thus the stack has been a popular target by many attacks and exploits like stack smashing attacks and return-oriented programming (ROP).
Yangchun Fu +5 more
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Defense against Stack-Based Attacks Using Speculative Stack Layout Transformation
Runtime Verification, 2012This paper describes a novel technique to defend binaries against intra-frame stack-based attacks, including overflows into local variables, when source code is unavailable. The technique infers a specification of a function’s stack layout, i.e., variable locations and boundaries, and then seeks to apply a combination of transformations, including ...
Benjamin D. Rodes +5 more
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Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible.
W. Luk, A. Dean
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Optimum stacked layout for analog CMOS ICs
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002 A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms.
E. Malavasi +2 more
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Stack and Queue Layouts of Directed Acyclic Graphs: Part II
SIAM Journal on Computing, 1999 Summary: Stack layouts and queue layouts of undirected graphs have been used to model problems in fault tolerant computing and in parallel process scheduling. However, problems in parallel process scheduling are more accurately modeled by stack and queue layouts of directed acyclic graphs (dags).
Lenwood S. Heath, Sriram V. Pemmaraju
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Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits
Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology, 2003 This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed.
Ashok Raman, Marek Turowski, M.F. Mar
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Stack layout transformation: Towards diversity for securing binary programs
2012 34th International Conference on Software Engineering (ICSE), 2012Benjamin D. Rodes
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Analysis and optimization of module layout for multi-stack vanadium flow battery module
Journal of Power Sources, 2019 Hui Chen +5 more
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