Results 251 to 260 of about 726,600 (314)

An Innovative variable layout steam plant for waste heat recovery from marine dual-fuel engines

Ships and Offshore Structures, 2022
The paper describes an original Waste Heat Recovery (WHR) variable layout plant to produce steam from the exhaustgases of marine dual-fuel engines. A large part of the steam feeds an electric turbogenerator to improve the ship's energy efficiency.The ...
M. Altosole, U. Campora, Luigia Mocerino, R. Zaccone   +3 more
semanticscholar   +1 more source

On Families of Planar DAGs with Constant Stack Number

International Symposium Graph Drawing and Network Visualization, 2021
A $k$-stack layout (or $k$-page book embedding) of a graph consists of a total order of the vertices, and a partition of the edges into $k$ sets of non-crossing edges with respect to the vertex order.
M. Nöllenburg, S. Pupyrev
semanticscholar   +1 more source

Full stacked layout of analogue cells

IEEE International Symposium on Circuits and Systems, 2003
A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors.
U. Gatti, F. Maloberti, V. Liberali
openaire   +1 more source

Stack and Queue Layouts of Directed Acyclic Graphs: Part I

SIAM Journal on Computing, 1993
Summary: Stack layouts and queue layouts of undirected graphs have been used to model problems in fault-tolerant computing and in parallel process scheduling. However, problems in parallel process scheduling are more accurately modeled by stack and queue layouts of directed acyclic graphs (dags).
Heath, Lenwood S., Pemmaraju, Sriram V., Trenk, Ann N.   +2 more
openaire   +1 more source

Space-efficient layouts for block stacking warehouses

IISE Transactions, 2019
In block stacking warehouses, pallets of Stock Keeping Units (SKUs) are stacked on top of one another in lanes on the warehouse floor.
Shahab Derhami, Jeffrey S. Smith, Kevin R. Gue   +2 more
openaire   +1 more source

Automatic generation of transistor stacks for cmos analog layout

1993 IEEE International Symposium on Circuits and Systems, 2002
A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function ...
V. Liberali, E. Malavasi, D. Pandini
openaire   +1 more source

Building Layout Reconstruction in Concealed Human Target Sensing via UWB MIMO Through-Wall Imaging Radar

IEEE Geoscience and Remote Sensing Letters, 2018
This letter is devoted to the layout reconstruction via the ultra-wideband (UWB) through-wall imaging radar under one single observation and simultaneously takes account of the real-time human indication.
Yongping Song, Jun Hu, Ning Chu, T. Jin, Jianwen Zhang, Zhimin Zhou   +5 more
semanticscholar   +1 more source

Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing

International Interconnect Technology Conference, 2018
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduced to
A. Yeoh, A. Madhavan, N. Kybert, S. Anand, J. Shin, M. Asoro, S. Samarajeewa, J. Steigerwald, C. Ganpule, M. Buehler, A. Tripathi, V. Souw, M. Haran, S. Nigam, V. Chikarmane, P. Yashar, T. Mule, Y-H. Wu, K. Lee, M. Aykol, K. Marla, P. Sinha, S. Kirby, H. Hiramatsu, W. Han, M. Mori, M. Sharma, H. Jeedigunta, M. Sprinkle, C. Pelto, M. Tanniru, G. Leatherman, K. Fischer, I. Post, C. Auth   +34 more
semanticscholar   +1 more source

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

ACS Nano
A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high ...
Yifan Liu, Sujuan Ding, Weili Li, Zirui Zhang, Z. Pan, Yumeng Ze, Bing Gao, Yanning Zhang, Chuanhong Jin, L. Peng, Zhiyong Zhang   +10 more
semanticscholar   +1 more source

Stack and Queue Layouts for Toruses and Extended Hypercubes

2010 43rd Hawaii International Conference on System Sciences, 2010
Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses.
S. Bettayeb, M. H. Heydari, L. Morales, I. H. Sudborough   +3 more
openaire   +1 more source