Results 61 to 70 of about 108,706 (192)
AIP Advances, 2015 Si solar cells with a SiGe graded buffer on top are fabricated as the initial step in GaAsP/Si tandem cell fabrication. Using this structure, the impact of the SiGe buffer layer on the Si solar cells is characterized. To mitigate the impact of the narrow-
Evelina Polyzoeva +3 more
doaj +1 more source
Ta/CoFeB/MgO analysis for low power nanomagnetic devices
AIP Advances, 2020 The requirement of high memory bandwidth for next-generation computing systems moved the attention to the development of devices that can combine storage and logic capabilities.
F. Riente +5 more
doaj +1 more source
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout [PDF]
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009 The technology of through-silicon vias (TSVs) enables fine-grained integration of multiple dies into a single 3-D stack. TSVs occupy significant silicon area due to their sheer size, which has a great effect on the quality of 3-D integrated chips (ICs).
Dae Hyun Kim +2 more
openaire +1 more source
Low loss, high contrast optical waveguides based on CMOS compatible LPCVD processing: technology and experimental results [PDF]
, 2005 A new class of integrated optical waveguide structures is presented, based on low cost CMOS compatible LPCVD processing. This technology allows for medium and high index contrast waveguides with very low channel attenuation.
Borreman, A. +5 more
core +1 more source
On the Theory of Spatial and Temporal Locality [PDF]
, 2005 This paper studies the theory of caching and temporal and spatial locality. We show the following results: (1) hashing can be used to guarantee that caches with limited associativity behave as well as fully associative cache; (2) temporal locality cannot
Snir, Marc, Yu, Jing
core
CUP: Comprehensive User-Space Protection for C/C++
, 2017 Memory corruption vulnerabilities in C/C++ applications enable attackers to execute code, change data, and leak information. Current memory sanitizers do no provide comprehensive coverage of a program's data. In particular, existing tools focus primarily
Akritidis Periklis +4 more
core +1 more source
Layout Decomposition for Quadruple Patterning Lithography and Beyond
, 2014 For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this paper, we propose a generic
Pan, David Z., Yu, Bei
core +1 more source
Stack Layout Randomization with Minimal Rewriting of Android Binaries
, 2016 Stack-based attacks typically require that attackers have a good understanding of the stack layout of the victim program. In this paper, we leverage specific features on ARM architecture and propose a practical technique that introduces randomness to the stack layout when an Android application executes.
Liang, Yu +7 more
openaire +3 more sources
DR.SGX: Hardening SGX Enclaves against Cache Attacks with Data Location Randomization
, 2019 Recent research has demonstrated that Intel's SGX is vulnerable to software-based side-channel attacks. In a common attack, the adversary monitors CPU caches to infer secret-dependent data accesses patterns. Known defenses have major limitations, as they
Brasser, Ferdinand +5 more
core +1 more source
Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout
IEEE Journal of the Electron Devices Society, 2018 In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure.
Eisuke Anju +4 more
openaire +2 more sources