Results 271 to 280 of about 295,937 (324)

Nano-optomechanical static random access memory (SRAM)

2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
This paper reports an on chip nano-optomechanical SRAM, which is integrated with light modulation system on a single silicon chip. In particular, a doubly-clamped silicon beam shows bistability due to the non-linear optical gradient force generated from a ring resonator. The memory states are assigned with two stable deformation positions, which can be
B. Dong, H. Cai, Y. D. Gu, Z. C. Yang, Y. F. Jin, Y. L. Hao, D. L. Kwong, A. Q. Liu   +7 more
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A 128Kb CMOS static random-access memory

IBM Journal of Research and Development, 1991
This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip
J. L. Chu, H. R. Torabi, F. J. Towler
openaire   +1 more source

A static 4096-bit bipolar random-access memory

IEEE Journal of Solid-State Circuits, 1977
A description of a 23600 mil/SUP 2/, 35-ns 4096/spl times/1 bit bipolar RAM is presented. The historical evolution of density and performance of the 1024/spl times/1 forerunner along with advanced production and circuit techniques indicate the availability of an 11000 mil/SUP 2/, 10-ns, 4096/spl times/1 bipolar RAM by 1981.
W.H. Herndon, W. Ho, R. Ramirez
openaire   +1 more source

Low-power fast static random access memory cell

2010 International Conference on Computer Applications and Industrial Electronics, 2010
In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line.
C. M. R. Prabhu, Ajay Kumar Singh
openaire   +1 more source

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory

ACS Nano
Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three ...
Jiaona Zhang, Wanting Wang, Jiahao Zhu, Chunxiu Wang, Tianyu Zhu, Changbin Zhao, Jialiang Wang, Shengdong Zhang, Xinwei Wang, Kuan-Chang Chang, Hong Meng, Mansun Chan, Min Zhang   +12 more
openaire   +3 more sources

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Japanese Journal of Applied Physics, 2017
A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array.
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto   +5 more
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Design of static random access memory using QCA technology

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016
Quantum dot Cellular Automata(QCA) is one of the emerging trends in the field of nanotechnology which helps to overcome the limitations of CMOS technology. QCA can be used to design memory circuits. Static Random Access Memory (SRAM) is one of the attractive application of QCA technology.
D. Gracia Nirmala Rani, M. Saranya, T. Sivashankari, N. Meenakshi, R. Meena, S. Rajaram   +5 more
openaire   +1 more source

Static Random Access Memory Technologies

2009
This chapter contains sections titled: Basic SRAM Architecture and Cell Structures SRAM Selection Considerations High Performance SRAMs Advanced SRAM Architectures Low-Voltage SRAMs BiCMOS Technology SRAMs SOI SRAMs Specialty SRAMs This chapter contains sections titled ...
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Parallel testing of multi-port static random access memories

Microelectronics Journal, 2003
Abstract This paper presents a novel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory.
F. Karimi, S. Irrinki, T. Crosby, N. Park, F. Lombardi   +4 more
openaire   +1 more source

Design of ternary clocked adiabatic static random access memory

Journal of Semiconductors, 2011
Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the ...
Pengjun Wang, Fengna Mei
openaire   +1 more source