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Parallel testing of multi-port static random access memories for BIST
Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002Presents a built-in-self test (BIST) technique to implement the parallel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port ...
Farzin Karimi, Fabrizio Lombardi
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A realistic fault model and test algorithms for static random access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented.
Rob Dekker +2 more
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Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories
IEEE Journal of Solid-State Circuits, 2008Conventional memory address decoders based on static CMOS gates incur high clock loading and unnecessary power dissipation in unselected banks. This paper presents a dynamic word line decoder which is fast, has reduced active and leakage power dissipation, and also enables faster race-free sense timing.
Giby Samson +3 more
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Static Random Access Memory Failure Analysis
International Symposium for Testing and Failure AnalysisAbstract Presentation slides for the ISTFA 2025 Tutorial session “Static Random Access Memory Failure Analysis.”
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Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory
IEEE Transactions on Semiconductor Manufacturing, 2010In this paper, we examine the impact of random-dopant-fluctuation (RDF), process-variation-effect (PVE), and workfunction-fluctuation (WKF), on 16-nm-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells.
Yiming Li, Hui-Wen Cheng, Ming-Hung Han
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Reliability Improvement of Static Random Access Memory Bit-Cells
2019 International Conference on Smart Systems and Inventive Technology (ICSSIT), 2019The rapid growth in the semiconductor industry has paved the pathway for tremendous advancement in semiconductor memory technology. Internet of Things (IoT), wireless body sensor nodes and other high-end applications need power-efficient and reliable memories.
E.Jebamalar Leavline, A. Sugantha
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A bit cell for a static random access memory
2018According to an aspect of the present inventive concept there is provided a bit cell for a Static Random Access Memory, SRAM, the bit cell comprising: a first and a second vertical stack of transistors arranged on a substrate, each stack including: a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a ...
Weckx, Pieter +3 more
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Built-in Diagnostic Approaches for a Static Random Access Memory
2021 IEEE International Conference on Sensors and Nanotechnology (SENNANO), 2021Fanar Abass, Qais Al-Gayem
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