Results 271 to 280 of about 304,009 (317)
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On design of multiple-valued static random-access-memory
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
Okihiko Ishizuka +2 more
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High-speed GaAs static random-access memory
IEEE Transactions on Electron Devices, 1982An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert +3 more
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Parallel testing of multi-port static random access memories
Microelectronics Journal, 2003Abstract This paper presents a novel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory.
Farzin Karimi +4 more
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FAULT MODELING AND TESTING OF GaAs STATIC RANDOM ACCESS MEMORIES
1991, Proceedings. International Test Conference, 2005Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are ...
Sundarar Mohan, Pinaki Mazumder
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A realistic self-test machine for static random access memories
International Test Conference 1988 Proceeding@m_New Frontiers in Testing, 2003A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of ...
Frans P. M. Beenker +2 more
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Review of Sense Amplifiers for Static Random Access Memory
IETE Technical Review, 2013Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs).
Jiafeng Zhu, Na Bai, Jianhui Wu
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Random testing of multi-port static random access memories
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2003This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams.
Farzin Karimi +2 more
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Nano-optomechanical static random access memory (SRAM)
2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015This paper reports an on chip nano-optomechanical SRAM, which is integrated with light modulation system on a single silicon chip. In particular, a doubly-clamped silicon beam shows bistability due to the non-linear optical gradient force generated from a ring resonator. The memory states are assigned with two stable deformation positions, which can be
B. Dong +7 more
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A static 4096-bit bipolar random-access memory
IEEE Journal of Solid-State Circuits, 1977A description of a 23600 mil/SUP 2/, 35-ns 4096/spl times/1 bit bipolar RAM is presented. The historical evolution of density and performance of the 1024/spl times/1 forerunner along with advanced production and circuit techniques indicate the availability of an 11000 mil/SUP 2/, 10-ns, 4096/spl times/1 bipolar RAM by 1981.
W.H. Herndon, W. Ho, R. Ramirez
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A March-based fault location algorithm for static random access memories
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2003A March-based fault location algorithm is proposed for the repair of word-oriented static RAMs. A March CL algorithm of complexity 12N, N is the number of memory words, is defined for fault detection and partial diagnosis. A 3N or 4N March-like algorithm is used for location of the aggressor words of inter-word state, idempotent, inversion, write ...
Valery A. Vardanian, Yervant Zorian
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