Results 251 to 260 of about 52,126 (300)
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Applications in Static Random Access Memory (SRAM)
2016Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip.
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Static Random Access Memory Failure Analysis
International Symposium for Testing and Failure AnalysisAbstract Presentation slides for the ISTFA 2025 Tutorial session “Static Random Access Memory Failure Analysis.”
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A high-speed GaAs 1K static random access memory
IEEE Journal of Solid-State Circuits, 1985A high-performance 1024/spl times/1-bit static random access memory has been designed and fabricated using an epitaxial GaAs direct coupled logic process. Design rules include 4-/spl mu/m interconnect metallization lines and spaces with 2/spl times/4-/spl mu/m/SUP 2/ vias. MESFETS have 1-/spl mu/m gate length and a self-aligned source and drain.
P. O'Conner, P.G. Flahive, B.J. Roman
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Static random access memory using high electron mobility transistors
IEEE Electron Device Letters, 1984A 4-bit fully decoded static random access memory (RAM) has been designed and fabricated using high electron mobility transistors (HEMT's) with a direct-coupled FET logic approach. The circuit incorporates approximately 50 logic gates. A fully operating memory circuit was demonstrated with an access time of 1.1 ns and a minimum WRITE-enable pulse of ...
S.J. Lee +4 more
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4096 bit and larger bipolar static random access memories
Microelectronics Journal, 1980A description of a new 4096 bit, 600mw, 25ns, TAA static TTL RAM with a 2.3 mil 2 cell and a 17,200 mil 2 die is presented. The evolution of static bipolar RAMs is discussed along with an analysis of the power allocation of the current 600mW 4096 bit device. The use of PNP memory cell load devices and Darlington word drivers will lower overhead power
William H. Herndon, Wally Ho, Warren Ong
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A dynamic reconfiguration scheme for mega bit Static Random Access Memories
Microelectronics Reliability, 1994Abstract The objective of this paper is to present a novel dynamic reconfiguration scheme for mega bit Static Random Access Memories (SRAMs). Most of the conventional reconfiguration methods are implemented using two-way switching elements. The proposed scheme is based on on-chip word failure detection and reconfiguration to spare word cell using ...
Venkatapathi N. Rayapati +1 more
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Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory
IEEE Transactions on Semiconductor Manufacturing, 2010In this paper, we examine the impact of random-dopant-fluctuation (RDF), process-variation-effect (PVE), and workfunction-fluctuation (WKF), on 16-nm-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells.
Yiming Li, Hui-Wen Cheng, Ming-Hung Han
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A soft-error resilient low power static random access memory cell
Analog Integrated Circuits and Signal Processing, 2021Ashish Sachdeva, Vinay Tomar
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Trends in bipolar static random access memory (SRAM) design
Proceedings of the Bipolar Circuits and Technology Meeting, 2003A comparison of the high-performance static random access memories (SRAMs) of today to those of 20 years ago (1969) shows that the performance has been increased by a factor of 10 while costs have been improved by a factor of 100. An overview of SRAM circuits is provided, covering early configurations; ECL memory cells; alpha-particle soft errors ...
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Power Aware 10T Static Random-Access Memory Design
2023 2nd International Conference on Vision Towards Emerging Trends in Communication and Networking Technologies (ViTECoN), 2023Mooni Rahul +3 more
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