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Ultraflexible Monolithic Three-Dimensional Static Random Access Memory
ACS NanoFlexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three ...
Jiaona Zhang +2 more
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Testing static and dynamic faults in random access memories
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2003The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed,
Said Hamdioui +2 more
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On design of multiple-valued static random-access-memory
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
Okihiko Ishizuka +2 more
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High-speed GaAs static random-access memory
IEEE Transactions on Electron Devices, 1982An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert +3 more
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Random testing of multi-port static random access memories
Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2003This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams.
Farzin Karimi +2 more
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Parallel testing of multi-port static random access memories
Microelectronics Journal, 2003Abstract This paper presents a novel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory.
Farzin Karimi +4 more
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FAULT MODELING AND TESTING OF GaAs STATIC RANDOM ACCESS MEMORIES
1991, Proceedings. International Test Conference, 2005Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are ...
Sundarar Mohan, Pinaki Mazumder
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A realistic self-test machine for static random access memories
International Test Conference 1988 Proceeding@m_New Frontiers in Testing, 2003A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of ...
Frans P. M. Beenker +2 more
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A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors
Japanese Journal of Applied Physics, 1975A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as ...
S. Saito +5 more
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Review of Sense Amplifiers for Static Random Access Memory
IETE Technical Review, 2013Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs).
Jiafeng Zhu, Na Bai, Jianhui Wu
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