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International Journal of Circuit Theory and Applications, 2012
ABSTRACTThe cell static noise margin (SNM) is widely used as a stability criterion for static random‐access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM
José Luis Merino +3 more
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ABSTRACTThe cell static noise margin (SNM) is widely used as a stability criterion for static random‐access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM
José Luis Merino +3 more
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Static Random Access Memory Technologies
2009This chapter contains sections titled: Basic SRAM Architecture and Cell Structures SRAM Selection Considerations High Performance SRAMs Advanced SRAM Architectures Low-Voltage SRAMs BiCMOS Technology SRAMs SOI SRAMs Specialty SRAMs This chapter contains sections titled ...
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A March-based fault location algorithm for static random access memories
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2003A March-based fault location algorithm is proposed for the repair of word-oriented static RAMs. A March CL algorithm of complexity 12N, N is the number of memory words, is defined for fault detection and partial diagnosis. A 3N or 4N March-like algorithm is used for location of the aggressor words of inter-word state, idempotent, inversion, write ...
Valery A. Vardanian, Yervant Zorian
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A dynamic reconfiguration scheme for mega bit Static Random Access Memories
Microelectronics Reliability, 1994Abstract The objective of this paper is to present a novel dynamic reconfiguration scheme for mega bit Static Random Access Memories (SRAMs). Most of the conventional reconfiguration methods are implemented using two-way switching elements. The proposed scheme is based on on-chip word failure detection and reconfiguration to spare word cell using ...
Venkatapathi N. Rayapati +1 more
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A parallel approach for testing multi-port static random access memories
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2002This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory.
Farzin Karimi +3 more
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Minimal March Tests for Unlinked Static Faults in Random Access Memories
23rd IEEE VLSI Test Symposium (VTS'05), 2005New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002).
Gurgen Harutunyan +2 more
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Parallel testing of multi-port static random access memories for BIST
Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002Presents a built-in-self test (BIST) technique to implement the parallel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port ...
Farzin Karimi, Fabrizio Lombardi
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Applications in Static Random Access Memory (SRAM)
2016Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip.
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A realistic fault model and test algorithms for static random access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented.
Rob Dekker +2 more
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Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is
Heechai Kang +4 more
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