Results 201 to 210 of about 17,368,081 (283)

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

International journal of circuit theory and applications, 2022
This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime.
Abdolreza Darabi, M. Salehi, E. Abiri
semanticscholar   +1 more source

Design of a stable single sided 11T static random access memory cell with improved critical charge

International journal of numerical modelling, 2022
Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage.
Ashish Sachdeva
semanticscholar   +1 more source

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

International journal of circuit theory and applications, 2021
This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM).
Erfan Abbasian, Morteza Gholipour
semanticscholar   +1 more source

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

International journal of circuit theory and applications, 2021
Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain.
B. Rawat, P. Mittal
semanticscholar   +1 more source

A 32 nm single-ended single-port 7T static random access memory for low power utilization

Semiconductor Science and Technology, 2021
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while
B. Rawat, P. Mittal
semanticscholar   +1 more source

Single-Event Response of 22-nm Fully Depleted Silicon-on-Insulator Static Random Access Memory

IEEE Transactions on Nuclear Science, 2021
We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous ...
M. Casey, S. Stansberry, C. Seidleck, J. Maharrey, Dante Gamboa, J. Pellish, K. Label   +6 more
semanticscholar   +1 more source

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

International journal of circuit theory and applications, 2021
Graphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide‐semiconductor (MOS) transistor in future technologies.
Erfan Abbasian, Morteza Gholipour, Farzaneh Izadinasab   +2 more
semanticscholar   +1 more source

A 128Kb CMOS static random-access memory

IBM Journal of Research and Development, 1991
This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip
Jeff L. Chu, Hamid R. Torabi, Fred J. Towler   +2 more
openaire   +1 more source

A FinFET‐Based Low‐Power Static Random Access Memory Cell With Improved Stability

International journal of numerical modelling
This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits,
Gautam Rana, Ashish Sachdeva, M. Elangovan, Kulbhushan Sharma   +3 more
semanticscholar   +1 more source

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

J. Circuits Syst. Comput., 2020
This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation.
Ashish Sachdeva, V. Tomar
semanticscholar   +1 more source