Results 211 to 220 of about 17,368,081 (283)

Design and statistical analysis of low power and high speed 10T static random access memory cell

International journal of circuit theory and applications, 2020
Static random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems.
G. Prasad, N. Kumari, B. Mandi, Maifuz Ali   +3 more
semanticscholar   +1 more source

A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory.

Nanoscale Horizons, 2020
For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential ...
Kwan-Ho Kim, Hyung‐Youl Park, J. Shim, Gicheol Shin, Maksim Andreev, Jiwan Koo, Gwangwe Yoo, Kilsu Jung, K. Heo, Yoonmyung Lee, Hyun-Yong Yu, Kyung Rok Kim, J. Cho, Sungjoo Lee, Jin-Hong Park   +14 more
semanticscholar   +1 more source

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

Advanced Electronic Materials, 2019
Significant progress on carbon‐nanotube (CNT) electronics means that they are a serious candidate for use in high‐performance integrated circuits (ICs).
Maguang Zhu, Zhi-Yong Zhang, Lian-Mao Peng   +2 more
semanticscholar   +1 more source

Differential Spin Hall Effect-Based Nonvolatile Static Random Access Memory for Energy-Efficient and Fast Data Restoration Application

IEEE transactions on magnetics, 2019
Spintronics, being a burgeoning area of research, aims to incorporate magnetic tunnel junction (MTJ), as a basic storage building block, to various electronic applications.
S. Shreya, Brajesh Kumar Kaushik
semanticscholar   +1 more source

Low-power data encoding/decoding for energy-efficient static random access memory design

IET Circuits Devices Syst., 2019
This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that
G. Pasandi, Kolsoom Mehrabi, Behzad Ebrahimi, Sied Mehdi Fakhraei, A. Afzali-Kusha, M. Pedram   +5 more
semanticscholar   +1 more source

Random testing of multi-port static random access memories

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2003
This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams.
Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi   +2 more
openaire   +2 more sources

Testing static and dynamic faults in random access memories

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2003
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed,
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor   +2 more
openaire   +2 more sources

On design of multiple-valued static random-access-memory

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002
General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto   +2 more
openaire   +1 more source

High-speed GaAs static random-access memory

IEEE Transactions on Electron Devices, 1982
An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert, J.-P. Morin, G. Nuzillat, C. Arnodo   +3 more
openaire   +1 more source

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

AEU - International Journal of Electronics and Communications, 2023
Ashish Sachdeva, Deepak Kumar, Erfan Abbasian   +2 more
semanticscholar   +1 more source