Results 101 to 110 of about 12,245 (196)

Automated Synthesis of Multi-Port Memories and Control [PDF]

, 2019
Cirimelli-Low, Jesse, Grimes, Michael, Guthaus, Matthew R, Nichols, Hunter, Sowash, Jennifer   +4 more
core   +1 more source

Novel CPU cache architecture based on two-dimensional MTJ device with ferromagnetic Fe3GeTe2

AIP Advances
With the development of Artificial Intelligence (AI) in recent years, the fields of computer, biology, medicine, and aerospace have demanded higher requirements for the processing and storage of information.
Shaopu Han, Yanfeng Jiang
doaj   +1 more source

Review on Performance of Static Random Access Memory (SRAM)

IJARCCE, 2015
Santhiya. V, Mathan. N
openaire   +1 more source

A Study of Static Random Access Memory Single Event Effect (SRAM SEE) Test using 100 MeV Proton Accelerator

Journal of Space Technology and Applications, 2023
Wooje Han, Eunhye Choi, Kyunghee Kim, Seong-Keun Jeong   +3 more
openaire   +1 more source

Partitioned cache architectures for reduced NBTI-induced aging [PDF]

, 2011
Calimera, Andrea, Loghi, M., Macii, Enrico, Poncino, Massimo   +3 more
core   +1 more source

SRAM based Gaussian noise generation for post quantum cryptography. [PDF]

Sci Rep
Kim MS, Jeon SB, Kim S.
europepmc   +1 more source

Empirical Evaluation of Unoptimized Sorting Algorithms on 8-Bit AVR Arduino Microcontrollers. [PDF]

Sensors (Basel)
Golonka J, Krużel F.
europepmc   +1 more source

Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments. [PDF]

Micromachines (Basel)
Park SY, Jeong EG, Jo SH.
europepmc   +1 more source

Oxide Semiconductor Thin-Film Transistors for Low-Power Electronics. [PDF]

Adv Sci (Weinh)
Ren S, Huang Q, Li D, Wang S, Chen Y, Ren H, Wang Y, Tang Y, Zhu B.   +8 more
europepmc   +1 more source

An energy efficient processor array and memory controller for accurate processing of convolutional neural network-based inference engines. [PDF]

Sci Rep
Deepika S, Arunachalam V.
europepmc   +1 more source