Results 161 to 170 of about 12,245 (196)
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Failure analysis of die-attachment on static random access memory (SRAM) semiconductor devices
Journal of Electronic Materials, 1987Different combinations of the SRAM die and the substrates to yield a better die-attachment are studied. Cleanliness of die backside, plasma etching of contaminated die backside, new frames and old frames are the factors considered. The number of rejects due to die cracking in the die-attachment can be minimized if (1) production die and new frames are ...
S. L. Tan +3 more
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Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices
2014 IEEE Radiation Effects Data Workshop (REDW), 2014Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski +4 more
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Trends in bipolar static random access memory (SRAM) design
Proceedings of the Bipolar Circuits and Technology Meeting, 2003A comparison of the high-performance static random access memories (SRAMs) of today to those of 20 years ago (1969) shows that the performance has been increased by a factor of 10 while costs have been improved by a factor of 100. An overview of SRAM circuits is provided, covering early configurations; ECL memory cells; alpha-particle soft errors ...
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A novel high speed, three element Si-based static random access memory (SRAM) cell
IEEE Electron Device Letters, 1995A novel three element SRAM cell consisting of a gate, a load, and a bistable SiGe-Si diode as the storage element is proposed and demonstrated with a test structure. Containing two closely-spaced delta-doped layers and a SiGe-Si strained superlattice, the diode exhibits two stable states with a conductance contrast of over six orders of magnitude ...
T.K. Carns, X. Zheng, K.L. Wang
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Prompt and Total Dose Response of Hard 4k and 16k CMOS Static Random Access Memories (SRAMs)
IEEE Transactions on Nuclear Science, 1984The evolution of hardened CMOS memories has recently reached a milestone where the achieved bit density (16K bits/chip) is sufficiently large to warrant their application as an integral part of hardened systems, often replacing older memory technologies (e.g., magnetic core, plated wire, etc.) and achieving substantial performance (weight, power ...
A. A. Witteles +5 more
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JSTS:Journal of Semiconductor Technology and Science, 2015
As semiconductor devices are being scaled down, random variation becomes a critical issue, especially in the case of static random access memory (SRAM). Thus, there is an urgent need for statistical methodologies to analyze the impact of random variations on the SRAM.
Sangheon Oh +5 more
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As semiconductor devices are being scaled down, random variation becomes a critical issue, especially in the case of static random access memory (SRAM). Thus, there is an urgent need for statistical methodologies to analyze the impact of random variations on the SRAM.
Sangheon Oh +5 more
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Japanese Journal of Applied Physics, 1992
With the use of a single α particle of 3 MeV from a collimated micron-size ion beam, soft errors have been induced incidentally in 64 kbit SRAMs. Mapping of the soft error sites has revealed that the drain regions of “off”-state transistors are most susceptible to the single-ion hitting.
Katsunori Noritake +5 more
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With the use of a single α particle of 3 MeV from a collimated micron-size ion beam, soft errors have been induced incidentally in 64 kbit SRAMs. Mapping of the soft error sites has revealed that the drain regions of “off”-state transistors are most susceptible to the single-ion hitting.
Katsunori Noritake +5 more
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Applications in Static Random Access Memory (SRAM)
2016Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip.
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Japanese Journal of Applied Physics, 2003
The standby current at device off-state is investigated against the measuring mode in 6-T and low-power static random access memory (SRAM) device with short gate length of 0.12 µm and high density of 32 M-bit. It can be found that there is the difference of the standby currents between initial and D0 modes and this discrepancy in the standby current is
Sang-Hun Seo +3 more
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The standby current at device off-state is investigated against the measuring mode in 6-T and low-power static random access memory (SRAM) device with short gate length of 0.12 µm and high density of 32 M-bit. It can be found that there is the difference of the standby currents between initial and D0 modes and this discrepancy in the standby current is
Sang-Hun Seo +3 more
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IEEE Radiation Effects Data Workshop, 2005., 2005
Recent SEE testing of 1M and 4M monolithic SRAMs at Brookhaven National Laboratories has shown an extreme sensitivity to single-event latchup (SEL). We have observed SEL at the minimum heavy-ion LET available at Brookhaven, 0.375 MeV-cm/sup 2//mg.
T.E. Page, J.M. Benedetto
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Recent SEE testing of 1M and 4M monolithic SRAMs at Brookhaven National Laboratories has shown an extreme sensitivity to single-event latchup (SEL). We have observed SEL at the minimum heavy-ion LET available at Brookhaven, 0.375 MeV-cm/sup 2//mg.
T.E. Page, J.M. Benedetto
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