Results 11 to 20 of about 12,245 (196)

AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

open access: yesIET Circuits, Devices & Systems, 2017
Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8‐SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by ...
Ihsen Alouani   +4 more
openaire   +3 more sources

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

open access: yesJournal of Nanotechnology, 2020
The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects ...
Mathan Natarajamoorthy   +3 more
doaj   +1 more source

Improved reliability single loop single feed 7T SRAM cell for biomedical applications

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
Portable biomedical devices are born to reach a maximum number of people at an effective cost, and because of their small size and battery operation, the impact of portable medical devices is huge.
Ashish Panchal   +5 more
doaj   +1 more source

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

open access: yesNanoscale Research Letters, 2017
This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application.
Meng-Yin Hsu   +4 more
doaj   +1 more source

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

open access: yesIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019
High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spintransfer torque magnetic random access memory (STT-RAM), resistive ...
Dayane Reis   +11 more
doaj   +1 more source

Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells [PDF]

open access: yes, 2008
The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors.
Di Carlo, Stefano   +3 more
core   +1 more source

Investigating SRAM PUFs in large CPUs and GPUs [PDF]

open access: yes, 2015
Physically unclonable functions (PUFs) provide data that can be used for cryptographic purposes: on the one hand randomness for the initialization of random-number generators; on the other hand individual fingerprints for unique identification of ...
Bernstein, Daniel J.   +2 more
core   +10 more sources

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory

open access: yesSensors, 2023
This paper comparatively reviews sensing circuit designs for the most widely used embedded memory, static random-access memory (SRAM). Many sensing circuits for SRAM have been proposed to improve power efficiency and speed, because sensing operations in ...
Sangheon Lee   +2 more
doaj   +1 more source

Simulation Analysis and Performance Comparison for the Memory Cells [PDF]

open access: yesJournal of Electrical and Electronics Engineering, 2021
Leakage power dissipation is an important concern in ultra-deep submicron (ultra-DSM) regime because of the scaling of the technology node. The designing of the efficient memory cell is mandatory for the today’s portable applications.
SHARMA Vijay Kumar
doaj  

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation [PDF]

open access: yes, 2005
Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs.
Asenov, A.   +4 more
core   +1 more source

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