Static random access memory sram

Results 81 to 90 of about 12,245 (196)

Complementary Logic Driven by Dielectrophoretic Assembly of 2D Semiconductors

Advanced Functional Materials, Volume 36, Issue 11, 5 February 2026.
Scalable, parallel fabrication of complementary logic gates is demonstrated using electric‐field‐driven deterministic assembly of electrochemically exfoliated 2D n‐type MoS2 and p‐type WSe2 nanosheets. This strategy yields MoS2 and WSe2 transistors featuring average mobilities of 4.3 and 3.0 cm2 V−1 s−1, respectively, and on/off ratios of > 104 ...
Dongjoon Rhee +10 more
wiley +1 more source

Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling

Advances in Condensed Matter Physics, 2018
We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM).
S. Narendran, J. Selvakumar
doaj +1 more source

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

IEEE Access, 2019
A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation ...
Robert Giterman, Roman Golman, Adam Teman +2 more
doaj +1 more source

Ferroelectrics Hybrids: Harnessing Multifunctionality of 2D Semiconductors in the Post‐Moore Era

Advanced Materials, Volume 38, Issue 7, 2 February 2026.
In this Review, the state of art of ferroelectric hybrid systems—combining ferroelectrics, 2D semiconductors, and molecular switches is presented—as next‐generation platforms for high‐density, multifunctional electronics. By discussing 2D FeFET applications, nanoscale material downscaling, M3D integration, and emerging ferroelectrics, it highlights ...
Haixin Qiu +3 more
wiley +1 more source

SRAM-PUF Key Extraction Method and Performance Analysis Based on RS and BCH Codes [PDF]

Jisuanji gongcheng
The Physical Unclonable Function (PUF) is a unique and nonreplicable physical fingerprint formed by random deviations during chip manufacturing that can be used to identify individual chips.
Yu ZHOU, Zongguang YU
doaj +1 more source

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques [PDF]

Radioengineering, 2017
In this paper new write and read assist techniques, reduced coupling signal negative bitline (RCS-NBL) and low power disturbance noise reduction (LP-DNR) of 6T static random-access memory (SRAM) to improve its minimal supply voltage (VMIN), have been ...
S. Kumar, K. Saha, H. Gupta
doaj

Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell

International Journal of the Physical Sciences, 2012
In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and ...
openaire +1 more source

Multi-port Memory Design for Advanced Computer Architectures [PDF]

, 2013
In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters.
Zhao, Yirong
core

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

, 2019
Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip
Bol, David +2 more
core +1 more source

Efficient turbo product code decoder with Build‐In SRAM‐based transpose memory

Electronics Letters
Turbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random
Jianjun Luo +4 more
doaj +1 more source

sram
7. clean energy
leakage current

leakage power
low power
static random access memory

memory