Results 211 to 220 of about 129,221 (220)

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

Microprocessors and Microsystems, 2016
Wei-Kai Cheng
exaly  

Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy

Transactions on Architecture and Code Optimization, 2015
Gabriel Rodríguez, Juan Touriño, Mahmut Kandemir   +2 more
exaly  

STT-RAM Cell Optimization Considering MTJ and CMOS Variations

IEEE Transactions on Magnetics, 2011
Yaojun Zhang, Hai Li, Yiran Chen
exaly  

C1C

Transactions on Architecture and Code Optimization, 2013
Yaojun Zhang, Hai Li, Yiran Chen
exaly  

An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches

IEEE Transactions on Multi-Scale Computing Systems, 2018
Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi   +2 more
exaly  

Asymmetry of MTJ switching and its implication to STT-RAM designs

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Yaojun Zhang, Xiaobin Wang, Yong Li 0009, Alex K. Jones, Yiran Chen 0001   +4 more
openaire   +1 more source

The Prospect of STT-RAM Scaling From Readability Perspective

IEEE Transactions on Magnetics, 2012
Yaojun Zhang, Wujie Wen, Yiran Chen
exaly  

Shielding STT-RAM Based Register Files on GPUs against Read Disturbance

ACM Journal on Emerging Technologies in Computing Systems, 2017
Zhiguang Chen, Wanglei
exaly  

Periodic learning-based region selection for energy-efficient MLC STT-RAM cache

Journal of Supercomputing, 2019
Fanfan Shen, Yanxiang He, He Yanxiang
exaly  

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

IEEE Transactions on Computers, 2015
Qingan Li, Yanxiang He, Jianhua Li
exaly