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A low power STT-RAM based register file for GPGPUs
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016State-of-the-art general-purpose graphics processing units (GPGPUs) execute a large number of threads simultaneously to hide latency of memory hierarchy and functional units. The extreme multithreading requires a large register file to hold the state of the executing threads. As feature size shrinks, both static and dynamic power of SRAM based register
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The STeTSiMS STT-RAM simulation and modeling system
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011Clinton Wills Smullen IV +3 more
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Unleashing the potential of MLC STT-RAM caches
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013Xiuyuan Bi +3 more
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STT-RAM Designs Supporting Dual-Port Accesses
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013Xiuyuan Bi +2 more
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Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020Kyle Kuan, Tosiron Adegbija
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Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022Jen-Wei Hsieh
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Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010Yiran Chen, Hai Li, Haiwen Xi
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Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013Jianhua Li 0003 +5 more
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