Results 191 to 200 of about 129,221 (220)

Write-Amount-Aware Management Policies for STT-RAM Caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Spin-transfer torque random access memory (STT-RAM) technology has emerged as one of the most promising memory technologies owing to its nonvolatility, high density, and low-leakage power characteristics. However, STT-RAM has certain drawbacks such as high write energy consumption and limits to the number of write cycles.
Hyeonggyu Kim, Soontae Kim, Jooheung Lee
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Lower-bits cache for low power STT-RAM caches

2012 IEEE International Symposium on Circuits and Systems, 2012
As power-efficient design becomes more important, spin-transfer torque RAM (STT-RAM) has drawn a lot of attention due to its ability to meet both high performance and low power consumption. However, its high write energy incurs an increase of dynamic power consumption and may offset power saving due to its low static power.
Junwhan Ahn, Kiyoung Choi
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TENDRA: Targeted Endurance Attack on STT-RAM LLC

IEEE Embedded Systems Letters
Spin Transfer Torque RAM (STT-RAM) based Last Level Cache (LLC) offers significant benefits like high density and low refresh energy, but faces challenges like high write latency and limited endurance. Malicious attacks in a multi-core setup need access to only a single core to perform repeated attacks on specific memory locations that can lead to an ...
Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, Venkata Kalyan Tavva   +3 more
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Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access ...
Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen 0001   +3 more
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STT-RAM based energy-efficiency hybrid cache for CMPs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Modern high performance Chip Multiprocessor (CMP) systems rely on large on-chip cache hierarchy. As technology scales down, the leakage power of present SRAM based cache gradually dominates the on-chip power consumption, which can severely jeopardize system performance.
Jianhua Li 0003, Chun Jason Xue, Yinlong Xu 0001   +2 more
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Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

IEEE Transactions on Circuits and Systems II: Express Briefs, 2018
Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further.
Behzad Zeinali, Dimitrios Karsinos, Farshad Moradi   +2 more
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An efficient STT-RAM-based register file in GPU architectures

The 20th Asia and South Pacific Design Automation Conference, 2015
Modern GPGPUs employ a large register file (RF) to efficiently process heavily parallel threads in single instruction multiple thread (SIMT) fashion. The up-scaling of RF capacity, however, is greatly constrained by large cell area and high leakage power consumption of SRAM implementation.
Xiaoxiao Liu 0001, Mengjie Mao, Xiuyuan Bi, Hai Li 0001, Yiran Chen 0001   +4 more
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Giant Spin-Hall assisted STT-RAM and logic design

Integration, 2017
Abstract In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large programming energy of Magnetic Tunneling Junction (MTJ) continue being major challenges ...
Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001   +6 more
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Multiple Attempt Write Strategy for Low Energy STT-RAM

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic switching characteristics of STT-RAM write operation and propose a multiple-attempt write technique needed for it. In contrast to the traditional approach which uses the pulse that guarantees writes for all cells, the proposed technique uses multiple short pulses ...
Jaeyoung Park, Michael Orshansky
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Self-Terminated Write-Assist Technique for STT-RAM

IEEE Transactions on Magnetics, 2016
The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported ...
Mohit Kumar Gupta, Mohd. Hasan
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