Results 171 to 180 of about 183,725 (182)

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Kyle Kuan, Tosiron Adegbija
exaly  

A Study of STT-RAM-Based In-Memory Computing Across the Memory Hierarchy

2022
Tosiron Adegbija, Dhruv Gajaria
exaly  

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM

IEEE Transactions on Reliability, 2016
Weisheng Zhao, Jianlei Yang, Aida Todri-Sanial   +2 more
exaly  

Architecture and Data Migration Methodology for L1 Cache Design With Hybrid SRAM and Volatile STT-RAM Configuration

Microprocessors and Microsystems, 2016
Wei-Kai Cheng
exaly  

Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs

Computer Architecture News, 2011
Guangyu Sun, Yuan Xie, Chita R. Das
exaly  

Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches

2011
Mircea R Stan, Sudhanva Gurumurthi, Clinton W Smullen   +2 more
exaly  

An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors

IEEE Transactions on Parallel and Distributed Systems, 2017
Zahra Azad, Amir Mahdi Hosseini Monazzah, Hamed Farbeh   +2 more
exaly  

Asymmetry of MTJ switching and its implication to STT-RAM designs

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Yaojun Zhang, Xiaobin Wang, Yong Li 0009, Alex K. Jones, Yiran Chen 0001   +4 more
openaire   +1 more source

C1C

Transactions on Architecture and Code Optimization, 2013
Alex K. Jones, Yaojun Zhang, Yiran Chen
exaly  

A Design Guideline for Volatile STT-RAM With ECC and Scrubbing

2015
Kiyoung Choi, Namhyung Kim
exaly