Results 171 to 180 of about 168,024 (182)
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Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors
IEICE Electronics Express, 2018Hyukjun Lee, Hyunwoo Park
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Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Computer Architecture News, 2011Guangyu Sun, Yuan Xie, Chita Das
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A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy
2022Tosiron Adegbija, Dhruv Gajaria
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Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013Jianhua Li 0003 +5 more
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HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
IEEE Transactions on Computers, 2019Kyle Kuan, Tosiron Adegbija
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Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM
IEEE Transactions on Reliability, 2016Weisheng Zhao +2 more
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Periodic learning-based region selection for energy-efficient MLC STT-RAM cache
Journal of Supercomputing, 2019Fanfan Shen, Yanxiang He
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Asymmetry of MTJ switching and its implication to STT-RAM designs
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012Yaojun Zhang +4 more
openaire +1 more source
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches
IEEE Transactions on Multi-Scale Computing Systems, 2018Ryusuke Egawa +2 more
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