Results 171 to 180 of about 129,221 (220)
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STT-RAM Cache Hierarchy With Multiretention MTJ Designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint.
Xiuyuan Bi, Hai Li, Weng-Fai Wong
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Exploration of trade-offs in the design of volatile STT–RAM cache
Journal of Systems Architecture, 2016Abstract STT–RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT–RAM is inefficient in terms of energy and speed compared to SRAM and thus various device-/circuit-/architecture-level solutions have been proposed to tackle this inefficiency.
Namhyung Kim, Kiyoung Choi
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Exploring Applications of STT-RAM in GPU Architectures
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021Use of modern GPUs has been extended from traditional 3D graphic processing to computing acceleration of many scientific, engineering, and enterprise applications. In modern GPUs, on-chip memory capacity keeps increasing to support thousands of chip-resident threads.
Xiaoxiao Liu 0001 +4 more
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Proceedings of the International Conference on Computer-Aided Design, 2012
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ ...
Yaojun Zhang +4 more
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Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ ...
Yaojun Zhang +4 more
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Enhancing the lifetime of STT-RAM with MRU replacement algorithm
2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018Recent trends on Emerging Technologies of Non-Volatile Memory (NVM) were considered as better alternatives for SRAM. Spin-Transfer Torque Random Access Memory (STT-RAM) is a type of NVM having less leakage power and high cell density. Besides its advantages, NVM has low write endurance and high error rates.
Bhukya Krishna Priya +3 more
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When to forget: A system-level perspective on STT-RAMs
17th Asia and South Pacific Design Automation Conference, 2012The benefits of using STT-RAMs as an alternative to SRAMs are being examined in great detail. However their comparatively higher write latencies and energies continue to be roadblocks for migrating to MRAM based technology in memory hierarchies. In this paper, we present a novel method by which we demonstrate significant energy reduction in writing to ...
Karthik Swaminathan +3 more
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STT-RAM read stability in DRAM operating region
2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015Spin-transfer-torque RAM (STT-RAM) is the most promising candidate for replacing DRAM while gaining an additional function of non-volatility. The relationship between rapid increase of spin-inversion current and stability of read operation (read disturbance) in the DRAM-array operating time region of less than 10 ns (i.e., "fast" region) was examined ...
H. Kazama, Takayuki Kawahara
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A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the write time to a few nanoseconds and hence enabled the fast-switching STT-RAM (FS-STT-RAM).
Zhenyu Sun 0001, Hai Li 0001, Wenqing Wu
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Endurance enhancement of write-optimized STT-RAM caches
Proceedings of the International Symposium on Memory Systems, 2019Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high density, and near zero leakage, which are highly desired for on-chip caches.
Puneet Saraf, Madhu Mutyam
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Early eviction and swapping for MLC STT-RAM-based LLC
Proceedings of the 35th Annual ACM Symposium on Applied Computing, 2020Although Multi-Level Cell (MLC) Spin-Torque Transfer Random Access Memory (STT-RAM) can enlarge the cache capacity, it encounters write and read disturbance issues. In this paper, we propose early eviction to evict data in soft-ways earlier when we access hard-way data in high missrate sets.
Ping Cheng, Jen-Wei Hsieh
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