Results 161 to 170 of about 183,725 (182)

Self-Terminated Write-Assist Technique for STT-RAM

IEEE Transactions on Magnetics, 2016
The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported ...
Mohit Kumar Gupta, Mohd. Hasan
openaire   +1 more source

A low power STT-RAM based register file for GPGPUs

Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016
State-of-the-art general-purpose graphics processing units (GPGPUs) execute a large number of threads simultaneously to hide latency of memory hierarchy and functional units. The extreme multithreading requires a large register file to hold the state of the executing threads. As feature size shrinks, both static and dynamic power of SRAM based register
openaire   +1 more source

The STeTSiMS STT-RAM simulation and modeling system

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan   +3 more
openaire   +1 more source

Unleashing the potential of MLC STT-RAM caches

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li 0001   +3 more
openaire   +1 more source

The Prospect of STT-RAM Scaling

2017
Yaojun Zhang, Wujie Wen, Hai Li, Yiran Chen   +3 more
openaire   +1 more source

STT-RAM Designs Supporting Dual-Port Accesses

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013
Xiuyuan Bi, Mohamed Anis Weldon, Hai Li 0001   +2 more
openaire   +2 more sources

Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
Yiran Chen, Hai Helen Li, Yuan Yan
exaly  

Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013
Jianhua Li 0003, Liang Shi 0001, Qing'an Li, Chun Jason Xue, Yiran Chen 0001, Yinlong Xu 0001   +5 more
openaire   +2 more sources

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

IEEE Transactions on Computers, 2019
Kyle Kuan, Tosiron Adegbija
exaly  

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

IEEE Transactions on Computers, 2016
Soontae Kim, Hyeonggyu Kim, Hamed Farbeh
exaly