Results 161 to 170 of about 168,024 (182)

The STeTSiMS STT-RAM simulation and modeling system

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan   +3 more
openaire   +1 more source

Unleashing the potential of MLC STT-RAM caches

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li 0001   +3 more
openaire   +1 more source

The Prospect of STT-RAM Scaling

2017
Yaojun Zhang, Wujie Wen, Hai Li, Yiran Chen   +3 more
openaire   +1 more source

STT-RAM Designs Supporting Dual-Port Accesses

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013
Xiuyuan Bi, Mohamed Anis Weldon, Hai Li 0001   +2 more
openaire   +2 more sources

A cache consolidation design of MLC STT-RAM for energy efficiency enhancement on cyber-physical systems

ACM SIGAPP Applied Computing Review: A Publication of the Special Interest Group on Applied Computing, 2021
Hsin‐Wen Wei, Wei-Kuan Shih, Yuan-Hao Chang   +2 more
exaly  

Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy

Transactions on Architecture and Code Optimization, 2015
Juan Touriño, Gabriel Rodríguez, Mahmut Kandemir   +2 more
exaly  

Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

Microprocessors and Microsystems, 2016
Wei-Kai Cheng
exaly  

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Kyle Kuan, Tosiron Adegbija
exaly  

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

ACM Transactions on Design Automation of Electronic Systems, 2015
Hamid Sarbazi-Azad
exaly  

Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
Yiran Chen, Hai Li, Yuan Yan
exaly