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Write-Amount-Aware Management Policies for STT-RAM Caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017Spin-transfer torque random access memory (STT-RAM) technology has emerged as one of the most promising memory technologies owing to its nonvolatility, high density, and low-leakage power characteristics. However, STT-RAM has certain drawbacks such as high write energy consumption and limits to the number of write cycles.
Hyeonggyu Kim, Soontae Kim, Jooheung Lee
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Lower-bits cache for low power STT-RAM caches
2012 IEEE International Symposium on Circuits and Systems, 2012As power-efficient design becomes more important, spin-transfer torque RAM (STT-RAM) has drawn a lot of attention due to its ability to meet both high performance and low power consumption. However, its high write energy incurs an increase of dynamic power consumption and may offset power saving due to its low static power.
Junwhan Ahn, Kiyoung Choi
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Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access ...
Yaojun Zhang +3 more
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Giant Spin-Hall assisted STT-RAM and logic design
Integration, 2017Abstract In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large programming energy of Magnetic Tunneling Junction (MTJ) continue being major challenges ...
Enes Eken +6 more
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Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further.
Behzad Zeinali +2 more
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An efficient STT-RAM-based register file in GPU architectures
The 20th Asia and South Pacific Design Automation Conference, 2015Modern GPGPUs employ a large register file (RF) to efficiently process heavily parallel threads in single instruction multiple thread (SIMT) fashion. The up-scaling of RF capacity, however, is greatly constrained by large cell area and high leakage power consumption of SRAM implementation.
Xiaoxiao Liu 0001 +4 more
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Promoting MLC STT-RAM for the Future Persistent Memory System
2017 IEEE 15th Intl Conf on Dependable, Autonomic and Secure Computing, 15th Intl Conf on Pervasive Intelligence and Computing, 3rd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech), 2017As the memory wall issue continues in the era of big data, researchers have been exploring emerging technologies to replace or complement the current DRAM based main memory system. Among them, Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM) attracts tremendous interests and has been deployed as the onchip ...
Xunchao Chen +2 more
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Multiple Attempt Write Strategy for Low Energy STT-RAM
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016In this paper, we demonstrate an energy-reduction strategy that exploits the stochastic switching characteristics of STT-RAM write operation and propose a multiple-attempt write technique needed for it. In contrast to the traditional approach which uses the pulse that guarantees writes for all cells, the proposed technique uses multiple short pulses ...
Jaeyoung Park, Michael Orshansky
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Self-Terminated Write-Assist Technique for STT-RAM
IEEE Transactions on Magnetics, 2016The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported ...
Mohit Kumar Gupta, Mohd. Hasan
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A low power STT-RAM based register file for GPGPUs
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016State-of-the-art general-purpose graphics processing units (GPGPUs) execute a large number of threads simultaneously to hide latency of memory hierarchy and functional units. The extreme multithreading requires a large register file to hold the state of the executing threads. As feature size shrinks, both static and dynamic power of SRAM based register
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