Results 141 to 150 of about 168,024 (182)

Enhancing the Lifetime of STT-RAM by IFTRP

Engineering Research Express
Abstract Spin Transfer Torque Random Access memory (STT-RAM) is a better alternative to overcome the shortcomings of the existing memory technologies. But, the implementation of STT-RAM memory technologies on the existing memory are limited due to its write restriction.
Bhukya Krishna Priya, Bhukya Krishna Naick, N Ramasubramanian   +2 more
openaire   +1 more source

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

IEEE Transactions on Computers, 2013
Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed.
Qing'an Li, Jianhua Li 0003, Liang Shi 0001, Chun Jason Xue, Yiran Chen 0001, Yanxiang He   +5 more
openaire   +2 more sources

An efficient STT-RAM last level cache architecture for GPUs

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. With the increase of processing cores count, larger on-chip memories are required. Due to its high density and low power characteristics, STT-RAM technology can be utilized in GPUs where numerous ...
Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad   +3 more
openaire   +1 more source

A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
Spin-transfer torque magnetic random access memory (STT-RAM) is one of the most promising candidates for next-generation on-chip memories. While STT-RAM offers high density, negligible leakage power, and fast access speed, it also suffers from read-disturbance errors , that is, read operations might accidentally change the value of the accessed memory
Fateme S. Hosseini, Chengmo Yang
openaire   +2 more sources

TENDRA: Targeted Endurance Attack on STT-RAM LLC

IEEE Embedded Systems Letters
Spin Transfer Torque RAM (STT-RAM) based Last Level Cache (LLC) offers significant benefits like high density and low refresh energy, but faces challenges like high write latency and limited endurance. Malicious attacks in a multi-core setup need access to only a single core to perform repeated attacks on specific memory locations that can lead to an ...
Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, Venkata Kalyan Tavva   +3 more
openaire   +3 more sources

Synthesis and Analysis of STT-RAM Switching Characteristics

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016
Spin transfer torque random access memory is a latest cutting edge memory technology which is suitable to be considered for universal memory. In Spin transfer torque random access memory, the magnetic state of magnetic tunneling junction is switched by passing the spin-polarized current through the junction.
Abdul Kadeer Moin, V. Sulochana, null Anurag   +2 more
openaire   +1 more source

Energy reduction for STT-RAM using early write termination

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too
Ping Zhou, Bo Zhao 0007, Jun Yang 0002, Youtao Zhang   +3 more
openaire   +1 more source

Early eviction and swapping for MLC STT-RAM-based LLC

Proceedings of the 35th Annual ACM Symposium on Applied Computing, 2020
Although Multi-Level Cell (MLC) Spin-Torque Transfer Random Access Memory (STT-RAM) can enlarge the cache capacity, it encounters write and read disturbance issues. In this paper, we propose early eviction to evict data in soft-ways earlier when we access hard-way data in high missrate sets.
Ping Cheng, Jen-Wei Hsieh
openaire   +2 more sources

STT-RAM based energy-efficiency hybrid cache for CMPs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Modern high performance Chip Multiprocessor (CMP) systems rely on large on-chip cache hierarchy. As technology scales down, the leakage power of present SRAM based cache gradually dominates the on-chip power consumption, which can severely jeopardize system performance.
Jianhua Li 0003, Chun Jason Xue, Yinlong Xu 0001   +2 more
openaire   +1 more source

Ternary cache: Three-valued MLC STT-RAM caches

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014
Spin-transfer torque random access memory (STT-RAM) has become a promising non-volatile memory technology for cache memories. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to enhance data density, but it suffers from low reliability of its read and write operations. In this paper, we propose a novel cache design called Ternary cache.
Seokin Hong, Jongmin Lee 0002, Soontae Kim   +2 more
openaire   +1 more source