Results 141 to 150 of about 183,725 (182)

Endurance enhancement of write-optimized STT-RAM caches

Proceedings of the International Symposium on Memory Systems, 2019
Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high density, and near zero leakage, which are highly desired for on-chip caches.
Puneet Saraf, Madhu Mutyam
openaire   +1 more source

STT-RAM Cache Hierarchy With Multiretention MTJ Designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint.
Zhenyu Sun 0001, Xiuyuan Bi, Hai Li 0001, Weng-Fai Wong, Xiaochun Zhu   +4 more
openaire   +2 more sources

Early eviction and swapping for MLC STT-RAM-based LLC

Proceedings of the 35th Annual ACM Symposium on Applied Computing, 2020
Although Multi-Level Cell (MLC) Spin-Torque Transfer Random Access Memory (STT-RAM) can enlarge the cache capacity, it encounters write and read disturbance issues. In this paper, we propose early eviction to evict data in soft-ways earlier when we access hard-way data in high missrate sets.
Ping Cheng, Jen-Wei Hsieh
openaire   +2 more sources

A Novel L1 Cache Based on Volatile STT-RAM

2016
Spin-transfer torque random access memory (STT-RAM) is one of the most promising substitutes for universal main memory and cache due to its excellent scalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit ...
Hongguang Zhang, Minxuan Zhang
openaire   +2 more sources

Enhancing the Lifetime of STT-RAM by IFTRP

Engineering Research Express
Abstract Spin Transfer Torque Random Access memory (STT-RAM) is a better alternative to overcome the shortcomings of the existing memory technologies. But, the implementation of STT-RAM memory technologies on the existing memory are limited due to its write restriction.
Bhukya Krishna Priya, Bhukya Krishna Naick, N Ramasubramanian   +2 more
openaire   +1 more source

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

IEEE Transactions on Computers, 2013
Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed.
Qing'an Li, Jianhua Li 0003, Liang Shi 0001, Chun Jason Xue, Yiran Chen 0001, Yanxiang He   +5 more
openaire   +2 more sources

A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
Spin-transfer torque magnetic random access memory (STT-RAM) is one of the most promising candidates for next-generation on-chip memories. While STT-RAM offers high density, negligible leakage power, and fast access speed, it also suffers from read-disturbance errors , that is, read operations might accidentally change the value of the accessed memory
Fateme S. Hosseini, Chengmo Yang
openaire   +2 more sources

An efficient STT-RAM last level cache architecture for GPUs

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. With the increase of processing cores count, larger on-chip memories are required. Due to its high density and low power characteristics, STT-RAM technology can be utilized in GPUs where numerous ...
Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad   +3 more
openaire   +1 more source

Synthesis and Analysis of STT-RAM Switching Characteristics

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016
Spin transfer torque random access memory is a latest cutting edge memory technology which is suitable to be considered for universal memory. In Spin transfer torque random access memory, the magnetic state of magnetic tunneling junction is switched by passing the spin-polarized current through the junction.
Abdul Kadeer Moin, V. Sulochana, null Anurag   +2 more
openaire   +1 more source

TENDRA: Targeted Endurance Attack on STT-RAM LLC

IEEE Embedded Systems Letters
Spin Transfer Torque RAM (STT-RAM) based Last Level Cache (LLC) offers significant benefits like high density and low refresh energy, but faces challenges like high write latency and limited endurance. Malicious attacks in a multi-core setup need access to only a single core to perform repeated attacks on specific memory locations that can lead to an ...
Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, Venkata Kalyan Tavva   +3 more
openaire   +3 more sources