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Adaptive Phoneme State Learning Architecture for Enhanced Speech Recognition Using Backpropagation Neural Network and Hidden Markov Model. [PDF]
F1000ResSiddalingappa R +8 more
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Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study. [PDF]
Micromachines (Basel)Taheri N, Tabrizchi S, Roohi A.
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Architecture design with STT-RAM: Opportunities and challenges
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016 The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has attracted a lot of interest from both academia and industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages, including non-volatility, low leakage power, SRAM comparable read ...
Ping Chi +5 more
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A Restore-Free Mode for MLC STT-RAM Caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019 Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption,
Muhammad Avais Qureshi +2 more
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A Novel L1 Cache Based on Volatile STT-RAM
Communications in Computer and Information Science, 2016Spin-transfer torque random access memory (STT-RAM) is one of the most promising substitutes for universal main memory and cache due to its excellent scalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit ...
Hongguang Zhang, Minxuan Zhang
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Read Performance: The Newest Barrier in Scaled STT-RAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015Spin-torque transfer RAM (STT-RAM), a promising alternative to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling down to 45 nm and below, in particular, process variation, introduce the previously unreported ...
Alex Jones, Yaojun Zhang, Yiran Chen
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Exploration of trade-offs in the design of volatile STT–RAM cache
Journal of Systems Architecture, 2016Abstract STT–RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT–RAM is inefficient in terms of energy and speed compared to SRAM and thus various device-/circuit-/architecture-level solutions have been proposed to tackle this inefficiency.
Kiyoung Choi, Namhyung Kim
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An Energy-Efficient Scheme for STT-RAM L1 Cache
2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013Spin-Transfer Torque RAM (STT-RAM) is a promising cache candidate studied frequently in recent years. Compared to the traditional SRAM, The STT-RAM is more promising for future on-chip caches due to STT-RAM's long endurance, low leakage, high density and high access speed.
Tianzhou Chen, Jianliang Ma
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Modeling STT-RAM fabrication cost and impacts in NVSim
2016 Seventh International Green and Sustainable Computing Conference (IGSC), 2016 Reducing power consumption of computational systems in the use-phase has become a significant focus to decrease thermal impacts and overall energy consumption of computing systems while having battery life benefits for increasingly mobile computing products.
Ismail Bayram +5 more
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