Results 161 to 170 of about 19,527 (187)

Functional 2D MoS₂ NEMS resonator array with independent electronic tunability based on mass transfer printing. [PDF]

Microsyst Nanoeng
Liu Z, Zhu L, Yuan S, Zhang Y, Zhang P, Cai Z, Liu L, Yang R.   +7 more
europepmc   +1 more source

Flexible complementary circuits operating at sub-0.5 V via hybrid organic–inorganic electrolyte-gated transistors

Proceedings of the National Academy of Sciences, 2021
Significance Electrolyte-gated transistor (EGT)–based inverter circuits are the basic building blocks of next-generation flexible electronic devices. However, constructing high-performance complementary inverters is challenging due to the unbalanced electrical performances of available p- and n-type EGT semiconducting materials.
Yao Yao, Wei Huang, Jianhua Chen, Gang Wang, Hongming Chen, Xinming Zhuang, Yibin Ying, Jianfeng Ping, Tobin J. Marks, Antonio Facchetti   +9 more
openaire   +2 more sources

Sub 0.5-V bulk-driven winner take all circuit based on a new voltage follower

Analog Integrated Circuits and Signal Processing, 2016
A new solution for a bulk-driven ultra-low-voltage winner take all (WTA) circuit is described. The WTA structure is based on a new voltage follower (VF) circuit which could also be used in other applications as a general purpose precise VF for sub 0.5-V operation.
Tomasz Kulej, Fabian Khateb
openaire   +1 more source

Super stack technique to reduce leakage power for sub 0.5-V supply voltage in VLSI circuits

International Conference on Sustainable Energy and Intelligent Systems (SEISCON 2011), 2011
Leakage current of CMOS circuits has become a major factor in very deep submicron regime. ITRS reports that leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small. In this paper a leakage reduction technique named "Super stack"for sub 0.5-V supply voltage has been ...
T.G. Reddy, K. Suganthi
openaire   +1 more source

A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation

IEICE Transactions on Electronics, 2005
This paper describes a speed-oriented ullralow-voltage and low-power SOI circuit technique based on a differential enhancementand depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-V th CMOS circuit block for noncritical path, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to ...
openaire   +1 more source

A 0.5-V, 3-mW, 54×54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345), 2003
K. Fujii, T. Douseki
openaire   +1 more source

High-performance multiplex drug-gated CAR circuits

Cancer Cell, 2022
Wilson W Wong
exaly  

Glioblastoma remodelling of human neural circuits decreases survival

Nature, 2023
Abrar Choudhury, Alexander Aabedi, Galina Schmunk   +2 more
exaly  

Gut–brain circuits for fat preference

Nature, 2022
MENGTONG LI, Zhengyuan Lu, Charles Zuker
exaly