Results 131 to 140 of about 6,570 (171)

A near-threshold memristive computing-in-memory engine for edge intelligence. [PDF]

Nat Commun
Wang L, Li W, Zhou Z, An J, Ye W, Li Z, Gao H, Hu H, Liu J, Chen X, Li L, Liu Q, Seok M, Dou C, Liu M.   +14 more
europepmc   +1 more source

Improved NaI(Tl) and CsI(Tl)Detector Arrays for Environmental Airborne Gamma Spectrometry: Technical Progress Report [PDF]

, 1999
Cresswell, A.J., Murphy, S., Sanderson, D.C.W.   +2 more
core  

Exploring subthreshold processing for next-generation TinyAI. [PDF]

Front Comput Neurosci
Nakhle F, Harfouche AH, Karam H, Tserolas V.   +3 more
europepmc   +1 more source

A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications. [PDF]

Sensors (Basel)
Kim NS.
europepmc   +1 more source

A Closed-Loop Ear-Worn Wearable EEG System with Real-Time Passive Electrode Skin Impedance Measurement for Early Autism Detection. [PDF]

Sensors (Basel)
Sheeraz M, Aslam AR, Drakakis EM, Heidari H, Altaf MAB, Saadeh W.   +5 more
europepmc   +1 more source

Seamless integration of CMOS microsensors into open microfluidic systems.

Lab Chip
Bounik R, Landolt AE, Lee J, Viswam V, Cardes F, Modena MM, Hierlemann A.   +6 more
europepmc   +1 more source

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Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

Journal of Nanoelectronics and Optoelectronics, 2020
This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%.
Sheng-Biao An, Li-Xin Zhao, Shi-Cong Yang, Tao An, Rui-Xia Yang   +4 more
openaire   +1 more source

An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011
An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5µm CMOS process and the active core area is 0.5*1.0 mm2. Measurement results show the A/D achieves 49.8dB peak
null Yafei Ye, null Liyuan Liu, null Fule Li, null Dongmei Li, null Zhihua Wang   +4 more
openaire   +1 more source