Results 61 to 70 of about 6,570 (171)

A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications [PDF]

open access: yes, 2012
A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution.
Chandrakasan, Anantha P., Yip, Marcus
core   +1 more source

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

open access: yesSensors, 2015
This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling
Min-Kyu Kim   +2 more
doaj   +1 more source

Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC [PDF]

open access: yes, 2014
In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented.
Arbet, D.   +3 more
core  

A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC

open access: yesIEEE Open Journal of the Solid-State Circuits Society
This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and $4\times $ – $36\times $ lower sampling capacitor
Sumukh Prashant Bhanushali   +1 more
doaj   +1 more source

Data conversion frontends for area-constrained applications: the wireless network-on-chip case [PDF]

open access: yes, 2018
Multicore architectures cover a wide technologic spectrum and it is on the vanguard for an unlimited number of applications. As technology keeps growing and number of cores per chip increases (reaching what nowadays is known as massive multicore ...
López Lao, Alejandro
core  

LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

open access: yes, 2018
We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs).
Dwyer, D. A.   +12 more
core   +1 more source

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems [PDF]

open access: yes, 2012
Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and ...
Chandrakasan, Anantha P.   +5 more
core   +1 more source

Microcontroller Power Consumption Measurement Based on PSoC

open access: yesTelfor Journal, 2016
Microcontrollers are often used as central processing elements in embedded systems. Because of different sleep and performance modes that microcontrollers support, their power consumption may have a high dynamic range, over 100 dB.
S. P. Janković, V. R. Drndarević
doaj   +1 more source

Study of voltage controlled oscillator based analog-to-digital converter [PDF]

open access: yes, 2011
A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits.
Adhikari, Soumalya   +2 more
core  

Enhancement of SAR Algorithm for Analog to Digital Converter [PDF]

open access: yes, 2015
Nowadays, the development of the IC technology resulted in a growth of digital systems. Thus, Analog to Digital converters have become important. The important criteria of an ADC are resolution, speed and power.
Mon Mon Thin   +2 more
core  

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