Results 241 to 250 of about 328,138 (300)

Systems on Chip

2012
This chapter introduces the main concepts related to the implementation of embedded systems on FPGA devices. Many of these concepts will appear during the case studies that are exposed in the next chapter.
Jean-Pierre Deschamps, Gustavo D. Sutter, Enrique Cantó   +2 more
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System on Chip Age

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers, 2002
One is now standing at the entrance gate of the System on Chip Age. The constant progress of VLSI technology enables many logical functions to be designed on one chip. Today, one can realize 32 bit CPU by using only 1/4 area of a chip. The real area is usually filled with the peripheral circuits, such as cache/main memory controller, registers, bus ...
K. Mori, H. Yamada, S. Takizawa
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Systems-on-Chip Testing

2011
The design cycle of a complex system has greatly improved since the advent of the core-based design paradigm. Nevertheless, as technology evolves, new problems become the focus of attention. Currently, industry seems to be on pace in terms of design productivity and time-to-market, but yield, power dissipation, and reliability issues are still a ...
Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski   +2 more
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System on Chip

2010
In the previous chapters, we discussed various digital architectures that each present a different trade-off between flexibility and specialization. The trend was from specialized towards more general and more flexible. In this chapter, we complete the discussion with a generic architecture-specialization concept.
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Multicore Systems on Chip

2013
This chapter discusses multicore architectures for DSP applications. We explain briefly the main challenges involved in future processor designs, justifying the need for thread level parallelism exploration, since instruction-level parallelism is becoming increasingly difficult and unfeasible to explore given a limited power budget.
Luigi Carro, Mateus Beck Rutzig
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System-on-Chip design

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), 2002
This tutorial is a general introduction to System-on-Chip (SoC) design. In the paper, we will discuss four areas: first, an overview of SoC including descriptions of the major approaches and motivating factors behind this development. Next, we will briefly summarise key design methodologies, processes and flows.
G. Martin, H. Chang
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Wireless systems-on-chip

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), 2002
The miniaturization of electronics for wireless applications has experienced a tremendous progress in recent years and is today one of the most challenging playgrounds in the semiconductor industry for the development of mixed-signal analog-digital integrated systems.
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AMULET3i-an asynchronous system-on-chip

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586), 2002
AMULETSi is the third generation asynchronous ARM-compatible microprocessor subsystem developed at the University of Manchester. It is internally modular, being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus.
Garside, J. D., Bainbridge, W. J., Bardsley, A., Clark, D. M., Edwards, D. A., Furber, S. B., Liu, J., Lloyd, D. W., Mohammadi, S., Pepper, J. S., Petlin, O., Temple, S., Woods, J. V.   +12 more
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Embedded Multiprocessor Systems-on-Chip Programming

IEEE Software, 2009
We have demonstrated the toolflow developed at IMEC for the MPEG-4 encoder on different platforms. In the future, we want to integrate the different tools in the flow even more, because they are mainly used separately today. Furthermore, we are in the process of validating the flow on more applications, particularly in the wireless-communication domain.
Mignolet J.-Y., Wuyts R.
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System on Chip (SOC) Design

2016
SOCs are complex density ASICs and need to be validated using the FPGAs. In the present scenario there is more demand for the FPGA prototyping to realize the ASICs. Single or multiple FPGA can be used to prototype the desired SOC functionality. This chapter focuses on the discussion on the SOC components, challenges, and the SOC design flow.
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