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A Novel Technique to Design GNRFET Based Ternary Logic Circuits for High-Performance Applications
Russian microelectronicsP. Venkatramana +4 more
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Systematic design strategy for DPL-based ternary logic circuit
International Journal of Nanoparticles, 2020Aloke Saha, Narendra Deo Singh
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Hybrid CMOS-PCM Ternary Logic for Digital Circuit Applications
IEEE Transactions on Nanotechnology, 2023Manoj Kumar, Manan Suri
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An Efficient Design Methodology for CNFET Based Ternary Logic Circuits
Inis, 2016C. Vudadha, P. Phaneendra, M. Srinivas
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<title>Ternary logical circuits</title>
SPIE Proceedings, 2005Vasile Degeratu +2 more
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Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits
Journal of VLSI circuits and systems, 2023openaire +1 more source
Design of Adder Circuits using GNRFETs in Ternary Logic
2025 7th International Conference on Intelligent Sustainable Systems (ICISS)Harivaram Shervani +5 more
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Design of GNRFET ternary circuits using pass transistor logic (PTL)
AIP Conference ProceedingsPasupuleti Naga Sudhakar +1 more
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The Power Efficient Ternary Logic Half Adder and Multiplier Designs Using the GNRFET Technology
Transactions on Electrical and Electronic MaterialsKuruva Mahesh, Syed Shameem
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