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Photonic Tightly Coupled Array
IEEE Transactions on Microwave Theory and Techniques, 2018We present the first demonstration of a tightly coupled array (TCA) excited by high-power photodiodes directly integrated onto the antenna substrate. As a complex electrical feed network is not required to feed the radiating elements, the design can realize ultra-wide bandwidth while improving upon the size, weight, and power of conventional electronic-
Matthew R. Konkol +6 more
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Events And Interrupts in Tightly Coupled Multiprocessors
IEEE Micro, 1985In a decentralized multiprocessor, events must be stored, queued, and acknowledged. This can be accomplished by implementing a special event receiver called a synapse and by utilizing several forms of acknowledge.
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directCell: Hybrid systems with tightly coupled accelerators
IBM Journal of Research and Development, 2009The Cell Broadband Engine® (Cell/B.E.) processor is a hybrid IBM PowerPC® processor. In blade servers and PCI Express® card systems, it has been used primarily in a server context, with Linux® as the operating system. Because neither Linux as an operating system nor a PowerPC processor-based architecture is the preferred choice for all applications ...
Hartmut Penner +4 more
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Prototyping and Programming Tightly Coupled Accelerators
2010A tightly coupled accelerator is specialized hardware attached to and controlled by a host processor. In this paper, we will discuss the features of tightly coupled accelerators and describe our programming model. We will show that our approach allows for the rapid prototyping and development of tightly coupled accelerators, using a worked out example ...
Eric Stotzer +3 more
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Performance analysis of tightly-coupled multiprocessor minicomputers
Microprocessing and Microprogramming, 1990Abstract The design of a multiprocessor computer system requires the solution of architectural problems, related both to the design of the machine and to the operating system, which are not found in monoprocessor systems. Moreover, to achieve the expected level of performance, an accurate balance between the CPU and the I/O subsystem is very ...
Pistolesi, Luca +2 more
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Modeling Architectural Support for Tightly-Coupled Accelerators
2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020As proposed accelerators target finer-grained chunks of computation and data movement, it becomes increasingly important to couple them tightly with the processor, avoiding long invocation delays. However, the large implementation design space of these Tightly-Coupled Accelerators (TCAs) makes it difficult to balance trade-offs between hardware ...
David J. Schlais +2 more
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Interconnection Network for Tightly Coupled Accelerators Architecture
2013 IEEE 21st Annual Symposium on High-Performance Interconnects, 2013In recent years, heterogeneous clusters using accelerators have entered widespread use in high-performance computing systems. In such clusters, inter-node communication between accelerators normally requires several memory copies via CPU memory, which results in communication latency that causes severe performance degradation.
Toshihiro Hanawa +3 more
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Curriculum Learning for Tightly Coupled Multiagent Systems
International Joint Conference on Autonomous Agents and Multiagent Systems, 2019In this paper, we leverage curriculum learning (CL) to improve the performance of multiagent systems (MAS) that are trained with the cooperative coevolution of artificial neural networks. We design curricula to progressively change two dimensions: scale (i.e. domain size) and coupling (i.e. the number of agents required to complete a subtask).
Golden Rockefeller +2 more
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Prototyping of Tightly Coupled Hardware/Software-Systems
Design Automation for Embedded Systems, 1997Verification and test issues raise the need for rapid prototyping of complex systems and especially hardware/software-systems. We tackle this problem by integration of hardware/software-codesign and prototyping. First we define the concept of the entire system architecture. This concept directs the hardware/software-partitioning process.
Wolfram Hardt, Wolfgang Rosenstiel
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A asynchronous buffering network for tightly coupled multiprocessors
Proceedings of the 3rd international conference on Supercomputing - ICS '89, 1989In order to reach high performance, many levels of parallelism should be exploited simultaneously on massively parallel architectures. The efficiency of a large system heavily depends on the interconnection between the processing elements and the memories: asynchronous buffering networks allow a high throughput of requests when independent tasks are ...
Yvon Jégou, André Seznec
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