Results 221 to 230 of about 11,438 (267)
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Device-level transient fault modeling
Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing, 2002This paper examines the accuracy of a discrete logic-level fault model often assumed in gate-level or discrete timing simulation. The analysis is done by comparing the faulty behavior predicted by the discrete model to that predicted by a circuit-level SPICE model whose accuracy is generally accepted. The comparison is made at both the subcircuit level,
Gregory L. Ries +2 more
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Logic Circuits Testing for Transient Faults
European Test Symposium (ETS'05), 2005Transient faults are becoming an increasingly serious concern for logic circuits. They can be caused by thermal neutrons, present at all altitudes, and by other types of ionizing radiation, especially in aerospace applications and nuclear engineering. In this paper we examine issues related to detection of transient errors.
Smita Krishnaswamy +2 more
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Transient Fault Tolerance in Digital Systems
IEEE Micro, 1994It is hard to shield systems effectively from transient faults (fault avoidance techniques). So some other means must be employed to assure appropriate levels of transient fault tolerance (insensitivity to transient faults). They are based on fault-masking and fault recovery ideas.
exaly +2 more sources
Diagnosis of Transient Faults in Quantised Systems
IFAC Proceedings Volumes, 2000Abstract This paper concerns the diagnosis and identification of faults that occur in systems where signals can only be measured through a quantiser. A qualitative model is used that represents the discrete-event behaviour of the quantised system. Three different diagnostic algorithms are presented for determining the fault probabilities, the first ...
F. Schiller, J. Schröder, J. Lunze
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Transient fault analysis of CORDIC processor
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012In this paper, we propose a method to evaluate the impact of a transient fault in CORDIC processors. The proposed approach takes into account the spatial and temporal localization of the fault. It also embeds the probability that such a fault occurs. By defining a fault impact coefficient, it is possible to identify the most critical arithmetic blocks ...
Ting An +3 more
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Transient Fault Tolerance for ccNUMA Architecture
2012 Sixth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2012Transient fault is a critical concern in the reliability of microprocessors system. The software fault tolerance is more flexible and lower cost than the hardware fault tolerance. And also, as architectural trends point toward multi core designs, there is substantial interest in adapting parallel and redundancy hardware resources for transient fault ...
Xingjun Zhang +5 more
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Transient Fault Detection in State-Automata
2nd International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX '07), 2007State automata are implemented in numerous ways and technologies - from simple traffic light controls to high-performance microprocessors comprising thousands of different states. Highly-integrated microprocessors get more and more susceptible to transient faults induced by radiation, extreme clocking, temperature and decreasing voltage supplies.
Bernhard Fechner, Andre Osterloh
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Analog transient concurrent fault simulation with dynamic fault grouping
Proceedings 2000 International Conference on Computer Design, 2002Fast analog fault simulation is critical in test development and fault diagnosis for analog and mixed-signal circuits. It has been demonstrated that concurrent fault simulation methods can greatly reduce the computational complexity of analog fault simulation by sharing intermediate simulation results between different faults.
Junwei Hou, Abhijit Chatterjee
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Modelling the Effect of Transient Faults in Fault Tolerant Computer Systems
IFAC Proceedings Volumes, 1985Abstract The Bounded Set Approach to reliability modelling is extended to the case of transient faults in Fault Tolerant Systems. An arbitrary arrival time distribution is assumed for transient faults rather than a constant rate. The method has been automated and results of several studies are given.
Y. W. Yak +2 more
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Autonomous transient fault emulation on FPGAs for accelerating fault grading
11th IEEE International On-Line Testing Symposium, 2005Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Therefore, hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past.
Celia López-Ongil +3 more
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