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TSV repairing for 3D ICs using redundant TSV
2017 7th International Symposium on Embedded Computing and System Design (ISED), 2017Three dimensional integrated circuit (3D IC) based on through-silicon-via (TSV) is gaining significant importance in semiconductor industry. During manufacturing process there may have some faulty TSVs. Recovery of these faulty TSVs is necessary for a reliable TSV based system.
Sudeep Ghosh +3 more
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Hollow TSV VS solid TSV and the effect of medium filling in the hollow TSV
2013 14th International Conference on Electronic Packaging Technology, 2013This paper focuses on the effect to the transmission characteristic of the hollow TSV. Three parts will be figured out to make it around using the high frequency structure simulator: first, the variation of radius and length of the hollow portion; second, the change of the position of hollow portion; the last, the effect to the transmission performance
Ning Jianye +3 more
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2019 International 3D Systems Integration Conference (3DIC), 2019
The mismatch in thermal expansion coefficient (TEC) between copper and silicon causes serious problems in three-dimensional (3D) packaging. The common problem is TSV pumping when TSV is exposed to high temperature (400oC-600oC) during the wiring process. The copper pumping destroys wiring above TSV and leads to the failure of electronic devices.
Quy Dinh, Kazuo Kondo, Tetsuji Hirato
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The mismatch in thermal expansion coefficient (TEC) between copper and silicon causes serious problems in three-dimensional (3D) packaging. The common problem is TSV pumping when TSV is exposed to high temperature (400oC-600oC) during the wiring process. The copper pumping destroys wiring above TSV and leads to the failure of electronic devices.
Quy Dinh, Kazuo Kondo, Tetsuji Hirato
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TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test
2021 IEEE 39th VLSI Test Symposium (VTS), 2021As semiconductor technology develops, threedimensions integrated circuits (3-D ICs) is thought as a viable solution to further improve the performance of ICs. Throughsilicon-vias (TSVs) are the most important device in 3-D ICs. Therefore, TSVs testing is a very critical flow in 3-D ICs manufacturing.
Kangkang Xu, Yang Yu 0015, Xiyuan Peng
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Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs
IEEE Transactions on Computers, 2016TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in order to support better performance. This paper explores the challenges brought on by capacitive and inductive TSV-to-TSV coupling in TSV-based 3D ICs.
Pooria M. Yaghini +4 more
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Fault-tolerant TSV by using scan-chain test TSV
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this paper, an architecture of TSV recovery by using scan-chain test TSV is proposed. With the architecture, only a small amount of redundant TSVs is required to be inserted. Extra TSV area that occurs by our method is much less than that of other
Fu-Wei Chen +2 more
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2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015
In this paper, we analyzes the coupling capacitance between TSV-TSV, TSV-Metal interconnects, and TSV-Active device. This paper presents a complete analysis of coupling capacitance of TSV-TSV structures. As TSV parasitic capacitance is less than other conventional IO structures' capacitance, therefore TSV technology results in lower I/O power ...
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In this paper, we analyzes the coupling capacitance between TSV-TSV, TSV-Metal interconnects, and TSV-Active device. This paper presents a complete analysis of coupling capacitance of TSV-TSV structures. As TSV parasitic capacitance is less than other conventional IO structures' capacitance, therefore TSV technology results in lower I/O power ...
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The Impedance Analysis of Multiple TSV-to-TSV
Journal of the Institute of Electronics and Information Engineers, 2016본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다.
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Integrated materials enabling TSV/3D-TSV
2009 59th Electronic Components and Technology Conference, 2009There is a consistence flux of miniaturization, value added functionality to IC packaging/modules driven by significant increase of mobile/networking products in the consumer market. The advanced packaging technologies, particularly TSV/3D-TSV approach is driving innovative design and novel applications.
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TSV-to-TSV Coupling Analysis and Optimization
2012In this chapter we study TSV-to-TSV coupling in 3D ICs [4]. A full-chip signal integrity (SI) analysis flow is developed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite the fact that TSV count is much smaller compared with the gate count.
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