Results 141 to 150 of about 8,987 (189)

The effect of TSV design parameters on the manufacturability of TSV interposers

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012
TSV interposer is expected to be the driving vehicle for 2.5-D IC integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult for one to justify whether a TSV design or an interposer design is manufacturable or not because we are still lack of experimental reliability data.
Y. S. Chan, null Hong Yu Li, null Xiaowu Zhang   +2 more
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Pre-bond TSV Test Through TSV Probing

2013
Chapter 3 discussed the need for pre-bond TSV test and explored cutting-edge research in TSV testing using BIST. Pre-bond testing allows for the detection of defects that are inherent in the manufacture of the TSV itself, such as impurities or voids, while post-bond testing detects faults caused by thinning, alignment, and bonding.
Brandon Noia, Krishnendu Chakrabarty
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TSV Developments

EDFA Technical Articles, 2012
Abstract The pace of development for 2.5-D packaging solutions appears to be accelerating as the timeline for the adoption of 3D through-silicon via (TSV) technology continues to slide. This column discusses the latest advancements in 2.5-D or interposer packaging technology and the growing number of applications.
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Impact of oxide liner properties on TSV Cu pumping and TSV stress

2015 IEEE International Reliability Physics Symposium, 2015
We investigated the impact of oxide liner elastic modulus and thickness on through-silicon via (TSV) Cu pumping and stress. A low-k dielectric liner showed a decrease in residual Cu pumping and TSV stress compared to O 3 -TEOS SiO 2 and ALD SiO 2 liners.
Joke De Messemaeker, O. Varela Pedreira, A. Moussa, Nabi Nabiollahi, Kris Vanstreels, Stefaan Van Huylenbroeck, Harold Philipsen, Patrick Verdonck, Bart Vandevelde, Ingrid De Wolf, Eric Beyne, Kris Croes   +11 more
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TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications, and TSV-Based Bandpass Filter

2014
This chapter presents a novel design and characterization of the spiral inductor based on through silicon via (TSV) technology. An equivalent lumped model is introduced where this model is based on physics and takes into consideration TSV nonlinearities and skin effect.
Khaled Salah, Yehea Ismail, Alaa El-Rouby   +2 more
openaire   +1 more source

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

Proceedings of the 48th Design Automation Conference, 2011
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller com- pared with the gate count.
Chang Liu 0034, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim   +5 more
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Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

Journal of Electronic Materials, 2012
Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing ...
Heryanto, A., Putra, W. N., Trigg, Alastair David, Gao, S., Kwon, W. S., Che, Faxing, Ang, X. F., Wei, J., Made, Riko I., Gan, Chee Lip, Pey, Kin Leong   +10 more
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Methods to reduce thermal stress for TSV Scaling ∼TSV with novel structure: Annular-Trench-Isolated TSV

2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015
Through-Silicon Via (TSV) plays an important role as the interconnects in accomplishing three-dimensional miniaturization of electronic device. Due to large mismatch in Coefficients of Thermal Expansion (CTE) between metal via (usually copper) and silicon substrate of TSV, induced thermal stress would lead to electrical performance and various ...
Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi   +4 more
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TSV metrology and inspection challenges

2009 IEEE International Conference on 3D System Integration, 2009
The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen.
Ramakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira, Jan Vaes, Marc van Cauwenbergh, Anne Jourdain, Greet Verbinnen, Gino Marcuccilli, Glenn Florence, Shay Wolfling, Christine Pelissier, Haiping Zhang, Jaydeep Sinha, Andreas Machura, Irfan Malik   +15 more
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Simulation in 3D integration and TSV

2014 IEEE 5th Latin American Symposium on Circuits and Systems, 2014
The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions.
Kirsten Weide-Zaage, Aymen Moujbani, Jörg Kludt   +2 more
openaire   +1 more source