Results 201 to 209 of about 8,846,054 (209)

A method for the periodic boundary condition for thermo-elastic analysis of V-NAND flash memory structure

Mechanics of Advanced Materials and Structures
Yongha Kim, Seungjun Ryu, Sungryung Lee
openaire   +2 more sources

13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

IEEE International Solid-State Circuits Conference, 2019
Data storage is one of the hottest discussion topics in today’s connected world. The amount of data growth is expected to be exponential, while budget and space remain constricted. Since the transformation of storage device from planar NAND to 3D V-NAND [
Dongku Kang, Min-su Kim, Suchang Jeon, Won-Chang Jung, Jooyong Park, Gyo Soo Choo, Dong-Kyo Shim, Anil Kavala, Seungbum Kim, Kyung-Min Kang, Jiyoung Lee, K. Ko, H. Park, ByungJun Min, Changyeon Yu, Sewon Yun, Nahyun Kim, Y. Jung, S. Seo, Sunghoon Kim, M. Lee, Joonhong Park, James C. Kim, Young San Cha, Kwangwon Kim, Youngmin Jo, Hyun-Jin Kim, Youngdon Choi, J. Byun, Ji-hyun Park, Kiwon Kim, T. Kwon, Young-Sun Min, Chiweon Yoon, Youngcho Kim, Dong-Hun Kwak, Eungsuk Lee, Wook-Ghee Hahn, Kisung Kim, Kyungmin Kim, Euisang Yoon, Wontae Kim, I. Lee, Seunghyun Moon, Jeong-Don Ihm, D. Byeon, Ki-Whan Song, Sang-Jun Hwang, K. Kyung   +48 more
semanticscholar   +1 more source

Retention Improvement in Vertical NAND Flash Memory Using Electron Back-Tunneling

IEEE Electron Device Letters
We propose an electron back-tunneling (EBT) method to enhance the retention characteristics of vertical NAND (V-NAND) flash memory. The storage of back-tunneled electrons in the spacer region between adjacent cells is facilitated by the synergistic ...
Sungjun Park, Honam Yoo, Jong-Won Back, Joonhyung Cho, Yeongheon Yang, Jiseong Im, Ryun-Han Koo, J. Ko, Jong-Ho Lee   +8 more
semanticscholar   +1 more source

Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE)

IEEE Transactions on Electron Devices
In order to improve the reliability of vertical NAND (V-NAND) flash memory cells, a scheme using adaptive incremental step pulse programming (A-ISPP) and incremental step pulse erasing (ISPE) is proposed.
Sungjun Park, Honam Yoo, Yeongheon Yang, Jae-joon Kim, Jong-Ho Lee   +4 more
semanticscholar   +1 more source

Optimization of Programming Pulse Shape for Vertical NAND Flash Memory Using Neural Networks

IEEE Electron Device Letters
We optimize the shape of the pulse to maximally increase threshold voltage ( ${V}_{\text {th}}\text {)}$ during the incremental step pulse programming (ISPP) of vertical NAND (V-NAND) flash memory using neural networks (NNs). NN is trained using data on
Sungjun Park, Jaehyeon Kim, J. Ko, Jiseong Im, Yeongheon Yang, Jae-joon Kim, Jong-Ho Lee   +6 more
semanticscholar   +1 more source

On-Chip Learning in Vertical NAND Flash Memory Using Forward–Forward Algorithm

IEEE Transactions on Electron Devices
Unlike the previous ON-chip learning using backward propagation (BP) in vertical NAND (V-NAND) flash memory, a new approach utilizing only forward propagation (FP) is proposed.
Sungjun Park, J. Ko, In-Seok Lee, Ryun-Han Koo, Jeonghyun Kim, Yeongheon Yang, Dongseok Kwon, Jae-joon Kim, Jong-Ho Lee   +8 more
semanticscholar   +1 more source

Optimizing Memory Window for Ferroelectric Nand Applications: An Experimental Study on Dielectric Material Selection and Layer Positioning

IEEE Transactions on Electron Devices
We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) nand flash applications, with a total thickness budget of 18 nm.
Lance Fernandes, Prasanna Venkatesan Ravindran, Jiayi Chen, M. Tian, Dipjyoti Das, Hang Chen, W. Chern, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsu Kim, Wanki Kim, D. Ha, Shimeng Yu, S. Datta, A. Khan   +15 more
semanticscholar   +1 more source

Threshold Voltage Variations of 3D V-NAND Flash Memory Devices Due to Different Positions and Angles of the Single Grain Boundary

Journal of Nanoscience and Nanotechnology, 2017
Jun Gyu Lee, Keon-Ho Yoo, Tae Whan Kim
openaire   +1 more source

Effective Deep Learning Technology for Predicting High-Aspect Ratio Contact Hole Striation Problem in 3D V-NAND Flash Memory

Extended Abstracts of the 2025 International Conference on Solid State Devices and Materials
BYUNG YONG CHOI, HOYUN JUNG, JONGIK HONG, YOUNGCHAN PARK, BONG-TAE PARK, SEUNGWAN HONG, SUNG HOI HUR   +6 more
openaire   +1 more source