Results 11 to 20 of about 106,049 (265)

Anopheles mosquitoes reveal new principles of 3D genome organization in insects

open access: yesNature Communications, 2022
Anopheles mosquitoes are vectors of human malaria, and better understanding of them has implications for public health. Here, the authors apply Hi-C, FISH, RNA-seq, and ChIP-seq techniques to comprehensively characterize chromatin architecture and its ...
Varvara Lukyanchikova   +13 more
doaj   +1 more source

Robust high-dimensional memory-augmented neural networks

open access: yesNature Communications, 2021
The implementation of memory-augmented neural networks using conventional computer architectures is challenging due to a large number of read and write operations. Here, Karunaratne, Schmuck et al.
Geethan Karunaratne   +6 more
doaj   +1 more source

Out-of-order vector architectures [PDF]

open access: yesProceedings of 30th Annual International Symposium on Microarchitecture, 2002
Register renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is improved and available memory bandwidth is used more effectively.
Espasa Sans, Roger   +2 more
openaire   +1 more source

EfDenseNet: Automated Pulmonary Hypertension Detection Model Based on EfficientNetb0 and DenseNet201 Using CT Images

open access: yesIEEE Access, 2023
Pulmonary hypertension (PH) is a chronic and progressive disease. We introduced a novel automated self-organized feature engineering architecture for PH detection, which was trained and refined using a new thoracic CT image dataset.
Tarik Kivrak   +8 more
doaj   +1 more source

VECTORS — VidEo Communication Through Opportunistic Relays and Scalable video coding

open access: yesSoftwareX, 2019
Crowd-sourced video distribution is frequently of interest in the local vicinity. In this paper, we present a software platform called VECTORS to transfer videos over opportunistic networks with adaptive quality encoding to achieve reasonable delay ...
Abhishek Thakur   +2 more
doaj   +1 more source

Agent Collaborative Target Localization and Classification in Wireless Sensor Networks

open access: yesSensors, 2007
Wireless sensor networks (WSNs) are autonomous networks that have beenfrequently deployed to collaboratively perform target localization and classification tasks.Their autonomous and collaborative features resemble the characteristics of agents ...
Sheng Wang   +3 more
doaj   +1 more source

Lattice QCD on a novel vector architecture [PDF]

open access: yesProceedings of 37th International Symposium on Lattice Field Theory — PoS(LATTICE2019), 2020
Proceedings of Lattice 2019, 7 pages, 6 colorful figures (changed Fig. 6d) and its description)
Benjamin Huth, Nils Meyer, Tilo Wettig
openaire   +2 more sources

Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

open access: yesSensors, 2012
A novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper.
Wen-Jyi Hwang, Hui-Ya Li, Chien-Min Ou
doaj   +1 more source

Spectrograms of baleen whale records synthesized from Autoenconder architectures: CAE, VAE and CAE-LSTM

open access: yesRevista Elektrón, 2022
In this paper, different architectures of simple convolutional networks are analyzed to generate synthetic spectrograms corresponding to baleen whales. Simplicity in these models plays an important role in the implementations of these type of networks on
María Celeste Cabedio, Marco Carnaghi
doaj   +1 more source

Effective usage of vector registers in advanced vector architectures [PDF]

open access: yesProceedings 1997 International Conference on Parallel Architectures and Compilation Techniques, 2002
This paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the vector register length reduction with two different ILP techniques, decoupling and multithreading, the performance penalty can be made ...
Villa, Luis   +2 more
openaire   +1 more source

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