Results 261 to 270 of about 110,493 (310)

Vector architectures

Proceedings of the 12th international conference on Supercomputing, 1998
Vector architectures have long been the of choice for building supercomputers. They first appeared in the early aeventies and had a long period of unquestioned dominance from the time the CRAY-1 was introduced in 1976 until the the appearance of “killer micros”, in 1991.
Roger Espasa, Mateo Valero, James E. Smith 0001   +2 more
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The architecture of a homogeneous vector supercomputer

Journal of Parallel and Distributed Computing, 1986
A new homogeneous computer architecture developed by FPS combines two fundamental techniques for high-speed computing: parallelism based on the binary n-cube interconnect, and pipelined vector arithmetic. The design makes extensive use of VLSI technology, resulting in a processing node that can be economically replicated.
John L. Gustafson, Stuart Hawkinson, Ken Scott   +2 more
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VLSI architectures for vector quantization

Journal of VLSI signal processing systems for signal, image and video technology, 1995
The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem.
Yan, M., McCanny, J.V., Hu, Y.
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Systolic architectures for vector quantization

IEEE Transactions on Acoustics, Speech, and Signal Processing, 1988
The intensive computational demands of vector quantization (VQ) for important applications in speech and image compression and speech recognition have motivated the need for dedicated processors with very high throughput capabilities. Systolic architectures offer one of the most promising approaches for fulfilling the demanding VQ speed requirements in
Grant A. Davidson, Peter R. Cappello, Allen Gersho   +2 more
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Vector extensions to the VAX architecture

Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, 2002
The extension of the VAX architecture to include integrated vector processing is discussed. The design goals and constraints and an overview of the resulting architecture are presented. The architecture maximizes the asynchronism between the scalar and vector processors and the parallelism within the vector processor.
Dileep Bhandarkar, Richard Brunner
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Parallel architectures for vector quantization

Proceedings of International Conference on Neural Networks (ICNN'97), 2002
The paper describes a parallel implementation of neural networks based on vector quantization. A toroidal-mesh topology has been used to assess the overall approach. A theoretical analysis of the modular system's efficiency is presented. The final application goal is a lossy compression of high-dimensional data for low bit-rate communications ...
Ancona F, ROVETTA, STEFANO, ZUNINO, RODOLFO   +2 more
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Distributed vector architectures

Journal of Systems Architecture, 2000
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory.
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Vectorizing for a SIMdD DSP architecture

Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, 2003
The Single Instruction Multiple Data (SIMD) model for finegrained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demonstrate how SIMdD (SIMD on disjoint data) supports e#ective vectorization of digital signal processing (DSP) benchmarks, by facilitating data reorganization and reuse.
Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks   +3 more
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VAX vector architecture

Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90, 1990
The VAX Architecture has been extended to include an integrated, register-based vector processor. This extension allows both high-end and low-end implementations and can be supported with only small changes by VAX/VMS and VAX/ULTRIX operating systems. The extension is effectively exploited by the new vectorizing capabilities of VAX FORTRAN.
D. Bhandarkar, R. Brunner
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Vectorization of Architectural Floor Plans

2019 Twelfth International Conference on Contemporary Computing (IC3), 2019
This paper proposes a method to vectorize the architectural floor plans by recognizing the graphic primitives used in such drawings. The method consists of thin and thick layer separation of the input image, followed by the identification of thin lines, arcs, and circles.
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