Results 271 to 280 of about 110,493 (310)

Supporting matrix operations in vector architectures

Proceedings Sixth International Parallel Processing Symposium, 2003
Many elementary numerical algorithms involve not only vector operations but also matrix operations. Today's vector processors only support vector operations, and execute matrix operations in terms of vector operations, because they can not access matrix operands in one instruction. This will lead to poor sustained performances of vector machines.
Hua Bi, Wolfgang K. Giloi
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A Simulation Study of Decoupled Vector Architectures

The Journal of Supercomputing, 1999
Decoupling techniques can be applied to a vector processor, resulting in a large increase in performance of vectorizable programs. We simulate a selection of the Perfect Club and Specfp92 benchmark suites and compare their execution time on a conventional single port vector architecture with that of a decoupled vector architecture. Decoupling increases
Roger Espasa, Mateo Valero
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Compiling for an indirect vector register architecture

Proceedings of the 5th conference on Computing frontiers, 2008
The iVMX architecture contains a novel vector register file of up to 4096 vector registers accessed indirectly via a mapping mechanism, providing compatibility with the VMX architecture, and potential for dramatic performance benefits [7]. The large number of vector registers and the unique indirection mechanism pose compilation challenges to be used ...
Nuzman D., Namolaru M., Zaks A., Derby J.H.   +3 more
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Vector unit architecture for emotion synthesis

IEEE Micro, 2000
Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.
Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki   +13 more
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Concepts of the System/370 vector architecture

Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87, 1987
This paper discusses the performance, complexity and system-integration considerations that shaped the System/370 Vector Architecture [1, 9]. The architecture is intended for compatible systems providing a range of price and performance. The paper reviews the reasons for choosing a register-oriented architecture with compound instructions over storage ...
Brian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz   +3 more
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Towards an open architecture for vector GIS

Computers & Geosciences, 2006
A range of open source software tools are now available to the Geographical Information Systems (GIS) analyst. However these tools are not necessarily interoperable and rarely significantly interoperable with proprietary systems. The open architectures, which have been developed for web-oriented systems, together with those proposed by the Open ...
Robert I. Dunfey, Bruce M. Gittings, James K. Batcheller   +2 more
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The Architecture of Vector Control

Limn
Can bricks be made to breathe?
Elizabeth McCormick, Ann Kelly, Ibrahim Msuya   +2 more
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The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture

Programming and Computer Software, 2017
The complexity of software is ever increasing, and it requires more and more computational resources for its execution. A way to satisfy these requirements is the use of vector instructions that can operate with fixed-length vectors of data of the same.
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3D on-chip memory for the vector architecture

2009 IEEE International Conference on 3D System Integration, 2009
Vector supercomputers play an important roll in a high performance computing area because vector systems can achieve a high computational efficiency for large scale scientific applications. The most important factor of a vector supercomputer is its high memory bandwidth between the processor and the off-chip main memory.
Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi   +3 more
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A vector dataflow architecture

Proceedings. PARBASE-90: International Conference on Databases, Parallel Architectures, and Their Applications, 2002
The author presents a vector data-flow (VDF) architecture which is based on the following design philosophy: increasing data granularity, whenever possible, by grouping together ordered sequences of data into logical structures called vectors; increasing node granularity by grouping together nodes, according to a partitioning algorithm, to form logical
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