Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL. [PDF]
J Supercomput, 2023 de Castro M +4 more
europepmc +1 more source
Spike-based control monitoring and analysis with Address Event Representation [PDF]
, 2009 Neuromorphic engineering tries to mimic biological information processing. Address-Event Representation (AER) is a neuromorphic communication protocol for spiking neurons between different chips.
Berner, R. +4 more
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Automatisierte VHDL-Code-Generierung eines Delta-Sigma Modulators [PDF]
Advances in Radio Science, 2006 Im vorliegenden Beitrag wird eine automatische Generierung des VHDL-Codes eines Delta-Sigma Modulators präsentiert. Die Koeffizientenmultiplikation wird hierbei durch Bit-Serielle-Addition durchgeführt.
R. Spilka, T. Ostermann
doaj
Live Demonstration: On the distance estimation of moving targets with a Stereo-Vision AER system [PDF]
, 2012 Distance calculation is always one of the most important goals in a digital stereoscopic vision system. In an AER system this goal is very important too, but it cannot be calculated as accurately as we would like.
Domínguez Morales, Manuel Jesús +4 more
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ToPoliNano: Nano-magnet Logic Circuits Design and Simulation [PDF]
, 2013 Among the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are particularly interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such as a very low power ...
Frache, Stefano +3 more
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FPGAs Implementation of fast algorithms oriented to mp3 audio decompression
Revista Facultad de Ingeniería Universidad de Antioquia, 2012 La ejecución de los algoritmos de descompresión de audio exige procesadores potentes con alto nivel de desempeño, sin embargo, dichos algoritmos no son apropiados para aplicaciones óptimas en dispositivos móviles.
Antonio Benavides +2 more
doaj
High-Speed Hardware Architecture Based on Error Detection for KECCAK. [PDF]
Micromachines (Basel), 2023 Mestiri H, Barraj I.
europepmc +1 more source
Virtual Prototyping for Dynamically Reconfigurable Architectures using Dynamic Generic Mapping [PDF]
, 1998 This paper presents a virtual prototyping methodology for Dynamically Reconfigurable (DR) FPGAs. The methodology is based around a library of VHDL image processing components and allows the rapid prototyping and algorithmic development of low-level image
Gibson, Darrell +2 more
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Complex-Exponential-Based Bio-Inspired Neuron Model Implementation in FPGA Using Xilinx System Generator and Vivado Design Suite. [PDF]
Biomimetics (Basel), 2023 Ahmad M, Zhang L, Ng KTW, Chowdhury MEH.
europepmc +1 more source