Results 131 to 140 of about 425 (179)
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2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 2012
An all optical Viterbi decoder on a silicon chip was designed. The device is composed of an optical memory cell and two interfering input arms that use QPSK modulation to encode the incoming bits. The device has a shape of a ring resonator with a size of just a few micrometers and relies on the coupling of modes. Data processing of a few picoseconds is
Ted Frumkin, Amihai Meiri, Zeev Zalevsky
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An all optical Viterbi decoder on a silicon chip was designed. The device is composed of an optical memory cell and two interfering input arms that use QPSK modulation to encode the incoming bits. The device has a shape of a ring resonator with a size of just a few micrometers and relies on the coupling of modes. Data processing of a few picoseconds is
Ted Frumkin, Amihai Meiri, Zeev Zalevsky
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A parallel Viterbi decoding algorithm
Concurrency and Computation: Practice and Experience, 2001AbstractIn this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array.
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On the Viterbi decoding algorithm
IEEE Transactions on Information Theory, 1969A new interpretation of the Viterbi decoding algorithm based on the state-space approach to dyamical systems is presented. In this interpretation the optimum decoder solves a generalized regulator control problem by dynamic programming techniques.
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A new transform algorithm for Viterbi decoding
IEEE Transactions on Communications, 1990Implementation of the Viterbi decoding algorithm has attracted a great deal of interest in many applications, but the excessive hardware/time consumption caused by the dynamic and backtracking decoding procedures make it difficult to design efficient VLSI circuits for practical applications.
Kuei-Ann Wen +2 more
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Efficient scalable architectures for Viterbi decoders
Proceedings of International Conference on Application Specific Array Processors (ASAP '93), 2002Viterbi decoders (VDs) are widely used today for the decoding of convolutional codes in forward error correction schemes. Efficient deeply pipelined VLSI architectures, the generalized cascade VD and the trellis pipeline-interleaving (TPI) VD are adaptable to a given data rate only to a limited extent.
Stefan Bitterlich, Heinrich Meyr
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List Viterbi decoding algorithms with applications
IEEE Transactions on Communications, 1994A list Viterbi decoding algorithm (LVA) produces a rank ordered list of the L globally best candidates after a trellis search. The authors present two such algorithms, (i) a parallel LVA that simultaneously produces the L best candidates and (ii) a serial LVA that iteratively produces the k/sup th/ best candidate based on knowledge of the previously ...
Nambi Seshadri, Carl-Erik W. Sundberg
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A high-throughput reconfigurable Viterbi decoder
2011 International Conference on Wireless Communications and Signal Processing (WCSP), 2011A reconfigurable Viterbi decoder with high throughput and low complexity is presented in this paper. The proposed Viterbi decoder supports constraint lengths ranging from 3–9, code rates in the range of 1/2–1/3, and arbitrary truncation lengths. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G ...
Rongchun Li +3 more
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Low Complexity SST Viterbi Decoder
IEEE Vehicular Technology Conference, 2006Reducing the complexity and power consumption of the Viterbi decoder is one of the important design goals for high throughput wireless systems. Recently, a low complexity decoding algorithm was proposed to reduce the average number of ACS (Add Compare Select) operation of the Viterbi algorithm (VA) using the information of syndrome.
Jin Jie, Chi-Ying Tsui
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Design of a super-pipelined Viterbi decoder
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required.
Lihong Jia +3 more
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Truncation length for Viterbi decoding
IEEE Transactions on Communications, 1991A bound is derived and analyzed for the bit error rate (BER) of a Viterbi decoder with survivor truncation. Estimates of the SNR (signal-to-noise ratio) loss on the AWGN (additive white Gaussian noise) channel due to truncation are obtained for convolutional codes. Larger truncation lengths are required than the smallest value that does not effectively
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