Results 141 to 150 of about 425 (179)
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A dynamically reconfigurable adaptive viterbi decoder
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02, 2002The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital communication channels. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy.
Sriram Swaminathan +3 more
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High performance Viterbi decoder design
Cluster Computing, 2018Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization.
V. Kavitha 0002, S. Mohanraj
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Design and Implementation of Viterbi Decoder with FPGAs
Journal of VLSI signal processing systems for signal, image and video technology, 1999In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on ...
M. Kivioja, Jouni Isoaho, L. Vänskä
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Viterbi algorithm motives in turbo decoding
IEEE Information Theory Workshop, 2005., 2005This work addresses the problem of decoding turbo convolutional codes. In particular, it is concerned with the question of how maximum likelihood sequence estimation (MLSE), in the shape of the Viterbi algorithm (VA), can be utilized in the framework of turbo decoding. It is shown that the conventional VA, which is a soft-input hard-output decoder, can
Michael Kerner, Ofer Amrani
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A fully synthesizable parameterized Viterbi decoder
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), 2003The Viterbi algorithm is widely used in digital communications. It realizes the maximum-likelihood decoding of convolutional codes received from a noisy channel. Depending on the application (terrestrial, digital modems, digital cellular telephone applications and others) a Viterbi decoder must be designed to respect specific requirements such as small
R. Burger +4 more
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A Reconfigurable Viterbi Decoder for a Communication Platform
2006 International Conference on Field Programmable Logic and Applications, 2006A new large constraint length, soft decision viterbi decoder fabric is presented for deployment using platform based system on chip methodologies. The decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11, and GSM.
Imran Ahmed 0001, Tughrul Arslan
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On the probability of symbol error in Viterbi decoders
IEEE Transactions on Communications, 1997An upper bound is derived on the probability that at least one of a sequence of B consecutive bits at the output of a Viterbi (1979) decoder is in error. Such a bound is useful for the analysis of concatenated coding schemes employing an outer block code over GF(2/sup B/) (typically a Reed-Solomon (RS) code), an inner convolutional code, and a symbol ...
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Sliding block Viterbi decoders in FPGA
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012In this paper, we analyze the design of sliding block Viterbi decoders in FPGA based on two proposed parallel Viterbi decoders with different area/performance ratios. Viterbi decoders for two wireless technologies were designed considering the proposed Viterbi decoders achieving reductions in resource utilizations of more than 50% compared to other ...
Mário P. Véstias +2 more
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An FPGA Scalable Parallel Viterbi Decoder
2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2018Viterbi decoders are an essential component in many embedded systems used for decoding streams of N data symbols over noisy channels. The decoding process is a sequential process wherein the decoder builds a trellis for N received symbols and then it traverses the trellis back computing the path in the trellis that implies the minimal amount of ...
Yosi Ben-Asher +4 more
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A Simple Interleaver for Use with Viterbi Decoding
IEEE Transactions on Communications, 1978An interleaver/de-interleaver can be used to improve the performance of a Viterbi decoder in the presence of bursty noise. This note describes the design and a method for testing block interleavers which can be used to combat the effects of periodic pulsed RFI.
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