Results 161 to 170 of about 121,840 (219)
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Information Sciences, 1984
A concept of an intelligent memory, called an adaptive associative system (AAS), is described from the system level down to the device level. The performance of an AAS is discussed by means of computer simulations in regard to text processing and pattern recognition, especially such outstanding features as fault tolerance, semantic association ...
Goser, Karl +2 more
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A concept of an intelligent memory, called an adaptive associative system (AAS), is described from the system level down to the device level. The performance of an AAS is discussed by means of computer simulations in regard to text processing and pattern recognition, especially such outstanding features as fault tolerance, semantic association ...
Goser, Karl +2 more
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IEEE Transactions on Advanced Packaging, 1997
A great goal of optics in computing is the eventual failure of electrical interconnects. This leads to two guiding principles for smart pixel technologies, which integrate optoelectronic devices to electronics for optical read-in/out. One, that the electronics be state-of-the-art, or, in other words, not compromised by the integration with ...
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A great goal of optics in computing is the eventual failure of electrical interconnects. This leads to two guiding principles for smart pixel technologies, which integrate optoelectronic devices to electronics for optical read-in/out. One, that the electronics be state-of-the-art, or, in other words, not compromised by the integration with ...
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Architecture and VLSI design of a VLSI neural signal processor
1993 IEEE International Symposium on Circuits and Systems, 2002A chip based on a scalable parallel systolic VLSI architecture has been designed for executing the compute-bound algorithmic primitives used by search and learning algorithms in neural networks and low level signal processing. The signal processor executes the algorithmic primitives and shared by all neural nets.
Ulrich Ramacher +3 more
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Optimization of VLSI allocation
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002Allocation is one of main tasks in the high level synthesis. It includes module selection, functional unit allocation, storage allocation and interconnection allocation. In this paper, we model the allocation problem as cluster analysis and apply a new algorithm, neighbor state transition (NST) algorithm, for cluster optimization. It is proved that the
Zhongli He, Dian Zhou
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1999
VLSI TECHNOLOGY Bipolar Technology B. Gunnar Malm, Jan V. Grahn and Mikael Ostling CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S.
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VLSI TECHNOLOGY Bipolar Technology B. Gunnar Malm, Jan V. Grahn and Mikael Ostling CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S.
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The VLSI Complexity of Sorting
IEEE Transactions on Computers, 1981The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power. Other adjustments to the model make it possible to compare pipelined and nonpipelined designs.
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IEEE Communications Magazine, 1993
Very-large-scale integration (VLSI) technology applications, developments, and markets in China are discussed. It is suggested that VLSI technology is gaining momentum in China, especially in the area of application specific integrated circuits (ASICs) development.
Chongxi Feng, Yichao Wang
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Very-large-scale integration (VLSI) technology applications, developments, and markets in China are discussed. It is suggested that VLSI technology is gaining momentum in China, especially in the area of application specific integrated circuits (ASICs) development.
Chongxi Feng, Yichao Wang
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IEEE Transactions on Computers, 1983
This paper surveys nine designs for VLSI circuits that compute N-element Fourier transforms. The largest of the designs requires O(N2 log N) units of silicon area; it can start a new Fourier transform every O(log N) time units. The smallest designs have about 1/Nth of this throughput, but they require only 1/Nth as much area.
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This paper surveys nine designs for VLSI circuits that compute N-element Fourier transforms. The largest of the designs requires O(N2 log N) units of silicon area; it can start a new Fourier transform every O(log N) time units. The smallest designs have about 1/Nth of this throughput, but they require only 1/Nth as much area.
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Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input ...
Ashok Vittal +4 more
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IEEE Transactions on Neural Networks, 1992
A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size.
Matthew S. Melton +3 more
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A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size.
Matthew S. Melton +3 more
openaire +2 more sources