Results 181 to 190 of about 121,840 (219)
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VLSI Processor Architecture

IEEE Transactions on Computers, 1984
A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler.
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A VLSI RISC

Computer, 1982
David A. Patterson 0001   +1 more
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VLSI in Communications

IEEE Journal on Selected Areas in Communications, 1985
John S. Thompson, Robert E. Owen
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Advances in bipolar VLSI

Proceedings of the IEEE, 1990
Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI ...
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Partition Sorts for VLSI

1983
A new class of sorting algorithms called partition sorts is presented. Partition sorts can be viewed as periodic 2d-primitive sorting networks. Periodic says that they are concatenations of identical comparator networks. 2d-primitive says that there is a planar layout for these algorithms such that communication is exclusively local.
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VLSI Layout as Programming

ACM Transactions on Programming Languages and Systems, 1983
Richard J. Lipton   +4 more
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VLSI Testing

Computer, 1984
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Measurements of a VLSI design

Proceedings of the nineteenth design automation conference on - DAC '82, 1982
John K. Ousterhout, David M. Ungar
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VLSI physics

Integration, 1983
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VLSI algorithms and architectures

2006
In this paper we consider the relationship between algorithms and parallel VLSI architectures. Starting from the premise that VLSI is the natural habitat for parallel algorithmics, we outline the desirable features of VLSI architectures. Next we discuss the notion of algorithmic paradigm, as the data transfer pattern of a class of specific algorithms ...
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