VLSI Design of Neural Networks
Ramacher U, Rückert U. VLSI Design of Neural Networks.
Ramacher, Ulrich, Rückert, Ulrich
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Advanced quantum computing-driven digital twin for energy and timing optimization in low-power VLSI circuits &IoT devices. [PDF]
Mujahid MM, Jose D.
europepmc +1 more source
A Simulation-based Redundancy Identification in Combinational Circuits
[[abstract]]©2007 VLSI-Redundancy removal is an important operation in combinational logic optimization. Traditional redundancy identification algorithms are based on automatic test pattern generation algorithms.
Yi-Yuan Huang;Chun-Yao Wang
core
Robust and compact reversible logic gate for low-power and high-performance computing. [PDF]
Rajput A +3 more
europepmc +1 more source
Design of (2, 1, N) parallel convolutional encodes for VLSI
The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and
Huang XL(黄晓莉), Duan MQ(段茂强)
core
Resistive switching memristors: structures, materials, fabrication techniques, and process challenges for VLSI integration. [PDF]
Singla R, Pant D, Nautiyal P, Painuly A.
europepmc +1 more source
An improved VLSI test economics analysis system
[[abstract]]Managers used to consider design for testability (DFT) as an overhead in development and produc- tion rather than an aid. We take a full considera- tion on the relation between DFT methodologies and cost/revenue models, and show that DFT may ...
J.-D. Lin;J.-M. Lu;C.-W. Wu
core
Low-power design and implementation of an enhanced I2C bus controller using open lane: from RTL to GDSII. [PDF]
K G, S A, V A, Velmurugan SN, M M.
europepmc +1 more source
An In-Ear Sleep Modulation SoC Featuring a CNN-LSTM Accelerator with Long-Kernel Memory Reuse and Runtime Dynamic Quantization. [PDF]
Xu Y +10 more
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Deep learning-based prediction of PFAS toxicity in zebrafish. [PDF]
Ramasamy K, Nallasamy V.
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