Results 131 to 140 of about 13,582,659 (253)

Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor. [PDF]

Sci Rep
Arora S, Tripathi SL, Wijayanto I, Saxena S.   +3 more
europepmc   +1 more source

Porous Triboelectric Nanogenerator for Load Sensing of Total Knee Replacement. [PDF]

IEEE ASME Trans Mechatron
Mahmoudi E, Redgrift AG, Salman E, Stanacevic M, Willing R, Towfighian S.   +5 more
europepmc   +1 more source

Hardware Accelerators for VLSI Design [PDF]

VLSI Design, 1996
openaire   +1 more source

An efficient method of modulo adder design for Digital Signal Processing applications. [PDF]

MethodsX
Kumar Singhal S, Kumar S, Kumar Patel S, Rao KA, Saxena G.   +4 more
europepmc   +1 more source

Design Considerations of an Analog Voltage Mode Readout Circuit for the CMOS-SOI-MEMS Gas Sensor Dubbed GMOS. [PDF]

Micromachines (Basel)
Bukshish EL, Bar-Lev S, Blank T, Nemirovsky Y.   +3 more
europepmc   +1 more source

Design and performance analysis of a vertically stacked gate-all-around nanosheet FET with embedded nanocavity for biosensing applications. [PDF]

Sci Rep
Prasanna RL, Karumuri SR, Sreenivasulu VB, Kondaveeti GS.   +3 more
europepmc   +1 more source

Optimized NCFET-based approximate multiplier for energy-aware image applications. [PDF]

Sci Rep
Srinivas MBR, Elango K.
europepmc   +1 more source

5th international conference on VLSI design — VLSI design '92

Integration, 1991
openaire   +1 more source

Recent Trends in Low Power VLSI Design

R. Sivakumar, D. Jothi
semanticscholar   +1 more source

Power Optimization of TENGs via Load Capacitance Sizing. [PDF]

IEEE Sens J
Hosseini M, Chahari M, Stanacevic M, Towfighian S, Willing R, Salman E.   +5 more
europepmc   +1 more source