Results 141 to 150 of about 9,664,784 (224)

VLSI Design

, 2018
openaire   +1 more source

Direct observation of intra-grain defect formation during local solid-phase epitaxy. [PDF]

Sci Rep
Tezura M, Asano T, Takaishi R, Tomita M, Saitoh M, Tanaka H.   +5 more
europepmc   +1 more source

Single-cell impedance sensing on integrated circuit chip for fast tumor diagnosis. [PDF]

Microsyst Nanoeng
Hui W, Chen L, Andaluz S, Zhong Y, Huang X, Shen R, Zhu Z, Ma H, Mak PI, Martins R, Wang P, Yi S, Wang W, Lei KM, Jia Y.   +14 more
europepmc   +1 more source

Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor. [PDF]

Sci Rep
Arora S, Tripathi SL, Wijayanto I, Saxena S.   +3 more
europepmc   +1 more source

Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit. [PDF]

Nat Commun
Lin S, Huang T, Yang N, Zheng X, Yang H, Yun HS, Turner G, Zhong Y, Zou J, Zhang K, Wu J, Grajal J, Lin YC, Xie KY, Wang H, Kong J, Guo J, Shen S, Zhang X.   +18 more
europepmc   +1 more source

VLSI Design

, 2008
openaire   +1 more source

An efficient method of modulo adder design for Digital Signal Processing applications. [PDF]

MethodsX
Kumar Singhal S, Kumar S, Kumar Patel S, Rao KA, Saxena G.   +4 more
europepmc   +1 more source

Voltage compensation of manufacturing errors applied to artificial band gaps in nanoscale transistor. [PDF]

Sci Rep
Aghajani A, Karsenty A.
europepmc   +1 more source

Design Considerations of an Analog Voltage Mode Readout Circuit for the CMOS-SOI-MEMS Gas Sensor Dubbed GMOS. [PDF]

Micromachines (Basel)
Bukshish EL, Bar-Lev S, Blank T, Nemirovsky Y.   +3 more
europepmc   +1 more source

VLSI design methodology.

, 2015
openaire   +1 more source